| Message ID | 20220627195506.403715-1-pdel@fb.com |
|---|---|
| Headers | show |
| Series | aspeed: Add I2C new register DMA slave mode support | expand |
> On Jun 27, 2022, at 12:54 PM, Peter Delevoryas <pdel@fb.com> wrote: > > Hey everyone, > > I'm sending a big patch series for this, but only the last commit is really > intended to be accepted right now. I'm just including the rest of them > because it depends on them for testing. > > Klaus's changes include the multi-master stuff in hw/i2c/core.c, and the old > register mode slave mode support. > > My series of patches includes a bunch of changes to eliminate most (if not > all) of the I2C errors reported by the fb OpenBIC firmware for fby35 > CraterLake Bridge Interconnect (BIC) (shortname: oby35-cl) upon startup. > > In particular, I needed to add the IC_DEVICE_ID to the isl voltage regulator > implementation, which required a fix to the pmbus implementation when > switching pages. We weren't resetting the buffer state when switching > pages there. > > I also added a placeholder implementation of the PECI controller, that does > almost nothing, but doesn't produce errors. > > I added the fby35-cpld, which oby35-cl queries using master-mode TX and RX > commands. > > And finally, I added an "intel-me" device (Intel Management Engine) that > attempts to respond to the first IPMB message sent by the BIC. I used this > to test the final patch, which I actually want to merge, the I2C new > register DMA slave mode support. > > All the patches except the last one can be ignored for now if you want, > again, I just included them for testing purposes. > > The final patch is pretty rough, but I wanted to start the review instead of > waiting too long. I expect the interrupt handling part will be > the main blocker. > Arg, I forgot to send a link to the reference image for oby35-cl: wget https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.17.01/Y35BCL.elf qemu-system-arm -machine oby35-cl -kernel Y35BCL.elf -nographic When it boots, it should look like this: [00:00:00.006,000] <inf> usb_dc_aspeed: select ep[0x81] as IN endpoint [00:00:00.006,000] <inf> usb_dc_aspeed: select ep[0x82] as IN endpoint [00:00:00.006,000] <wrn> usb_dc_aspeed: pre-selected ep[0x1] as IN endpoint [00:00:00.006,000] <wrn> usb_dc_aspeed: pre-selected ep[0x2] as IN endpoint [00:00:00.006,000] <inf> usb_dc_aspeed: select ep[0x3] as OUT endpoint *** Booting Zephyr OS build v00.01.05 *** Hello, welcome to yv35 craterlake 2022.25.1 BIC class type(class-1), 1ou present status(0), 2ou present status(0), board revision(0x1) [init_drive_type] sensor 0x14 post sensor read failed! [init_drive_type] sensor 0x30 post sensor read failed! [init_drive_type] sensor 0x39 post sensor read failed! ipmi_init [set_DC_status] gpio number(15) status(0) [set_post_status] gpio number(1) status(1) uart:~$ [00:00:00.680,000] <inf> kcs_aspeed: KCS3: addr=0xca2, idr=0x2c, odr=0x38, str=0x44 [00:00:00.686,000] <err> spi_nor_multi_dev: [1216][spi1_cs0]SFDP magic 00000000 invalid [00:00:00.686,000] <err> spi_nor_multi_dev: [1456]SFDP read failed: -22 [00:00:00.680,000] <inf> kcs_aspeed: KCS3: addr=0xca2, idr=0x2c, odr=0x38, str=0x44 [00:00:00.686,000] <err> spi_nor_multi_dev: [1216][spi1_cs0]SFDP magic 00000000 invalid [00:00:00.686,000] <err> spi_nor_multi_dev: [1456]SFDP read failed: -22 uart:~$ BIC Ready If the i2c patches aren’t included, then the BIC will be unable to get the initial ME IPMB response and print an error message: uart:~$ BIC Ready Failed to get ME self test result, ret: 0x8 > Thanks, > Peter > > Klaus Jensen (3): > hw/i2c: support multiple masters > hw/i2c: add asynchronous send > hw/i2c/aspeed: add slave device in old register mode > > Peter Delevoryas (11): > aspeed: i2c: Fix DMA len write-enable bit handling > aspeed: i2c: Fix R_I2CD_FUN_CTRL reference > aspeed: i2c: Fix MASTER_EN missing error message > aspeed: Add PECI controller > hw/misc: Add fby35-cpld > pmbus: Reset out buf after switching pages > pmbus: Add read-only IC_DEVICE_ID support > aspeed: Add oby35-cl machine > hw/misc: Add intel-me > aspeed: Add intel-me on i2c6 instead of BMC > aspeed: Add I2C new register DMA slave mode support > > hw/arm/aspeed.c | 42 ++++++ > hw/arm/aspeed_ast10x0.c | 11 ++ > hw/arm/pxa2xx.c | 2 + > hw/display/sii9022.c | 2 + > hw/display/ssd0303.c | 2 + > hw/i2c/aspeed_i2c.c | 234 +++++++++++++++++++++++++++---- > hw/i2c/core.c | 70 ++++++++- > hw/i2c/pmbus_device.c | 6 + > hw/i2c/smbus_slave.c | 4 + > hw/i2c/trace-events | 2 + > hw/misc/aspeed_peci.c | 225 +++++++++++++++++++++++++++++ > hw/misc/fby35_cpld.c | 137 ++++++++++++++++++ > hw/misc/intel_me.c | 176 +++++++++++++++++++++++ > hw/misc/meson.build | 5 +- > hw/nvram/eeprom_at24c.c | 2 + > hw/sensor/isl_pmbus_vr.c | 30 ++++ > hw/sensor/lsm303dlhc_mag.c | 2 + > include/hw/arm/aspeed_soc.h | 3 + > include/hw/i2c/aspeed_i2c.h | 11 ++ > include/hw/i2c/i2c.h | 30 ++++ > include/hw/i2c/pmbus_device.h | 1 + > include/hw/misc/aspeed_peci.h | 34 +++++ > include/hw/sensor/isl_pmbus_vr.h | 1 + > 23 files changed, 1002 insertions(+), 30 deletions(-) > create mode 100644 hw/misc/aspeed_peci.c > create mode 100644 hw/misc/fby35_cpld.c > create mode 100644 hw/misc/intel_me.c > create mode 100644 include/hw/misc/aspeed_peci.h > > -- > 2.30.2 >
On 6/27/22 21:54, Peter Delevoryas wrote: > Hey everyone, > > I'm sending a big patch series for this, but only the last commit is really > intended to be accepted right now. I'm just including the rest of them > because it depends on them for testing. > > Klaus's changes include the multi-master stuff in hw/i2c/core.c, and the old > register mode slave mode support. > > My series of patches includes a bunch of changes to eliminate most (if not > all) of the I2C errors reported by the fb OpenBIC firmware for fby35 > CraterLake Bridge Interconnect (BIC) (shortname: oby35-cl) upon startup. > > In particular, I needed to add the IC_DEVICE_ID to the isl voltage regulator > implementation, which required a fix to the pmbus implementation when > switching pages. We weren't resetting the buffer state when switching > pages there. > > I also added a placeholder implementation of the PECI controller, that does > almost nothing, but doesn't produce errors. > > I added the fby35-cpld, which oby35-cl queries using master-mode TX and RX > commands. > > And finally, I added an "intel-me" device (Intel Management Engine) that > attempts to respond to the first IPMB message sent by the BIC. I used this > to test the final patch, which I actually want to merge, the I2C new > register DMA slave mode support. > > All the patches except the last one can be ignored for now if you want, > again, I just included them for testing purposes. > > The final patch is pretty rough, but I wanted to start the review instead of > waiting too long. I expect the interrupt handling part will be > the main blocker. > > Thanks, > Peter > > Klaus Jensen (3): > hw/i2c: support multiple masters > hw/i2c: add asynchronous send > hw/i2c/aspeed: add slave device in old register mode > > Peter Delevoryas (11): > aspeed: i2c: Fix DMA len write-enable bit handling > aspeed: i2c: Fix R_I2CD_FUN_CTRL reference > aspeed: i2c: Fix MASTER_EN missing error message I didn't receive this patch ? C. > aspeed: Add PECI controller > hw/misc: Add fby35-cpld > pmbus: Reset out buf after switching pages > pmbus: Add read-only IC_DEVICE_ID support > aspeed: Add oby35-cl machine > hw/misc: Add intel-me > aspeed: Add intel-me on i2c6 instead of BMC > aspeed: Add I2C new register DMA slave mode support > > hw/arm/aspeed.c | 42 ++++++ > hw/arm/aspeed_ast10x0.c | 11 ++ > hw/arm/pxa2xx.c | 2 + > hw/display/sii9022.c | 2 + > hw/display/ssd0303.c | 2 + > hw/i2c/aspeed_i2c.c | 234 +++++++++++++++++++++++++++---- > hw/i2c/core.c | 70 ++++++++- > hw/i2c/pmbus_device.c | 6 + > hw/i2c/smbus_slave.c | 4 + > hw/i2c/trace-events | 2 + > hw/misc/aspeed_peci.c | 225 +++++++++++++++++++++++++++++ > hw/misc/fby35_cpld.c | 137 ++++++++++++++++++ > hw/misc/intel_me.c | 176 +++++++++++++++++++++++ > hw/misc/meson.build | 5 +- > hw/nvram/eeprom_at24c.c | 2 + > hw/sensor/isl_pmbus_vr.c | 30 ++++ > hw/sensor/lsm303dlhc_mag.c | 2 + > include/hw/arm/aspeed_soc.h | 3 + > include/hw/i2c/aspeed_i2c.h | 11 ++ > include/hw/i2c/i2c.h | 30 ++++ > include/hw/i2c/pmbus_device.h | 1 + > include/hw/misc/aspeed_peci.h | 34 +++++ > include/hw/sensor/isl_pmbus_vr.h | 1 + > 23 files changed, 1002 insertions(+), 30 deletions(-) > create mode 100644 hw/misc/aspeed_peci.c > create mode 100644 hw/misc/fby35_cpld.c > create mode 100644 hw/misc/intel_me.c > create mode 100644 include/hw/misc/aspeed_peci.h >
> On Jun 28, 2022, at 12:05 AM, Cédric Le Goater <clg@kaod.org> wrote: > > On 6/27/22 21:54, Peter Delevoryas wrote: >> Hey everyone, >> I'm sending a big patch series for this, but only the last commit is really >> intended to be accepted right now. I'm just including the rest of them >> because it depends on them for testing. >> Klaus's changes include the multi-master stuff in hw/i2c/core.c, and the old >> register mode slave mode support. >> My series of patches includes a bunch of changes to eliminate most (if not >> all) of the I2C errors reported by the fb OpenBIC firmware for fby35 >> CraterLake Bridge Interconnect (BIC) (shortname: oby35-cl) upon startup. >> In particular, I needed to add the IC_DEVICE_ID to the isl voltage regulator >> implementation, which required a fix to the pmbus implementation when >> switching pages. We weren't resetting the buffer state when switching >> pages there. >> I also added a placeholder implementation of the PECI controller, that does >> almost nothing, but doesn't produce errors. >> I added the fby35-cpld, which oby35-cl queries using master-mode TX and RX >> commands. >> And finally, I added an "intel-me" device (Intel Management Engine) that >> attempts to respond to the first IPMB message sent by the BIC. I used this >> to test the final patch, which I actually want to merge, the I2C new >> register DMA slave mode support. >> All the patches except the last one can be ignored for now if you want, >> again, I just included them for testing purposes. >> The final patch is pretty rough, but I wanted to start the review instead of >> waiting too long. I expect the interrupt handling part will be >> the main blocker. >> Thanks, >> Peter >> Klaus Jensen (3): >> hw/i2c: support multiple masters >> hw/i2c: add asynchronous send >> hw/i2c/aspeed: add slave device in old register mode >> Peter Delevoryas (11): >> aspeed: i2c: Fix DMA len write-enable bit handling >> aspeed: i2c: Fix R_I2CD_FUN_CTRL reference >> aspeed: i2c: Fix MASTER_EN missing error message > > > I didn't receive this patch ? Yes, sorry about that, the FB email filter is very delicate, the behavior is seemingly random to me. I’ve been trying to debug it. I re-sent 12-14 manually, but resending patch 6 didn’t work for some reason. I’ve been attempting to switch to a personal email, me@pjd.dev, but I can’t seem to get git-send-email working with it. It’s really ridiculous. Probably have to start bringing a personal laptop to the office. I’ve attempted to resend this patch, number 6, one more time, just now. I’ll include it again in v2, and hopefully I’ll have my email working at that point. > > C. > > >> aspeed: Add PECI controller >> hw/misc: Add fby35-cpld >> pmbus: Reset out buf after switching pages >> pmbus: Add read-only IC_DEVICE_ID support >> aspeed: Add oby35-cl machine >> hw/misc: Add intel-me >> aspeed: Add intel-me on i2c6 instead of BMC >> aspeed: Add I2C new register DMA slave mode support >> hw/arm/aspeed.c | 42 ++++++ >> hw/arm/aspeed_ast10x0.c | 11 ++ >> hw/arm/pxa2xx.c | 2 + >> hw/display/sii9022.c | 2 + >> hw/display/ssd0303.c | 2 + >> hw/i2c/aspeed_i2c.c | 234 +++++++++++++++++++++++++++---- >> hw/i2c/core.c | 70 ++++++++- >> hw/i2c/pmbus_device.c | 6 + >> hw/i2c/smbus_slave.c | 4 + >> hw/i2c/trace-events | 2 + >> hw/misc/aspeed_peci.c | 225 +++++++++++++++++++++++++++++ >> hw/misc/fby35_cpld.c | 137 ++++++++++++++++++ >> hw/misc/intel_me.c | 176 +++++++++++++++++++++++ >> hw/misc/meson.build | 5 +- >> hw/nvram/eeprom_at24c.c | 2 + >> hw/sensor/isl_pmbus_vr.c | 30 ++++ >> hw/sensor/lsm303dlhc_mag.c | 2 + >> include/hw/arm/aspeed_soc.h | 3 + >> include/hw/i2c/aspeed_i2c.h | 11 ++ >> include/hw/i2c/i2c.h | 30 ++++ >> include/hw/i2c/pmbus_device.h | 1 + >> include/hw/misc/aspeed_peci.h | 34 +++++ >> include/hw/sensor/isl_pmbus_vr.h | 1 + >> 23 files changed, 1002 insertions(+), 30 deletions(-) >> create mode 100644 hw/misc/aspeed_peci.c >> create mode 100644 hw/misc/fby35_cpld.c >> create mode 100644 hw/misc/intel_me.c >> create mode 100644 include/hw/misc/aspeed_peci.h >