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[v2,0/5] Implement Sstc extension

Message ID 20220426230855.336292-1-atishp@rivosinc.com
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Series Implement Sstc extension | expand

Message

Atish Kumar Patra April 26, 2022, 11:08 p.m. UTC 
This series implements Sstc extension[1] which was ratified recently.

The first patch is a prepartory patches while PATCH 2 adds stimecmp
support while PATCH 3 adds vstimecmp support. This series is based on
on top of upstream commit (faee5441a038).

The series can also be found at
https://github.com/atishp04/qemu/tree/sstc_v2

It is tested on RV32 & RV64 with additional OpenSBI[2] & Linux kernel[3]
patches.

Changes from v1->v2:
1. Rebased on the latest upstream commit.
2. Replaced PATCH 1 with another patch where mtimer/timecmp is
   moved from CPU to ACLINT.
3. Added ACLINT migration support.

[1] https://drive.google.com/file/d/1m84Re2yK8m_vbW7TspvevCDR82MOBaSX/view
[2] https://github.com/atishp04/opensbi/tree/sstc_v2
[3] https://github.com/atishp04/linux/tree/sstc_v3

Atish Patra (5):
hw/intc: Move mtimer/mtimecmp to aclint
migration: Add 64bit variable array data type
hw/intc: Support migration of aclint device
target/riscv: Add stimecmp support
target/riscv: Add vstimecmp support

hw/intc/riscv_aclint.c         |  41 +++++---
hw/timer/ibex_timer.c          |  20 ++--
include/hw/intc/riscv_aclint.h |   2 +
include/hw/timer/ibex_timer.h  |   2 +
include/migration/vmstate.h    |  11 ++
migration/vmstate.c            |   2 +
target/riscv/cpu.c             |   8 ++
target/riscv/cpu.h             |  10 +-
target/riscv/cpu_bits.h        |   8 ++
target/riscv/cpu_helper.c      |  11 +-
target/riscv/csr.c             | 181 +++++++++++++++++++++++++++++++++
target/riscv/machine.c         |   3 +-
target/riscv/meson.build       |   3 +-
target/riscv/time_helper.c     | 114 +++++++++++++++++++++
target/riscv/time_helper.h     |  30 ++++++
15 files changed, 415 insertions(+), 31 deletions(-)
create mode 100644 target/riscv/time_helper.c
create mode 100644 target/riscv/time_helper.h

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2.25.1