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[RFC,v2,0/3] Support ACLINT 32/64-bit mtimecmp/mtime read/write accesses

Message ID 20220210061737.1171-1-frank.chang@sifive.com
Headers show
Series Support ACLINT 32/64-bit mtimecmp/mtime read/write accesses | expand

Message

Frank Chang Feb. 10, 2022, 6:17 a.m. UTC 
From: Frank Chang <frank.chang@sifive.com>

This patchset makes ACLINT mtime to be writable as RISC-V privilege
spec defines that mtime is exposed as a memory-mapped machine-mode
read-write register. Also, mtimecmp and mtime should be 32/64-bit memory
accessible registers.

This patchset is the updated verion of:
https://patchew.org/QEMU/20220126095448.2964-1-frank.chang@sifive.com/

Changelog:

v2:
  * Support 32/64-bit mtimecmp/mtime memory accesses.
  * Add .impl.[min|max]_access_size declaration.

Frank Chang (3):
  hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT
  hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V
    ACLINT
  hw/intc: Make RISC-V ACLINT mtime MMIO register writable

 hw/intc/riscv_aclint.c         | 87 +++++++++++++++++++++++-----------
 include/hw/intc/riscv_aclint.h |  1 +
 target/riscv/cpu.h             |  8 ++--
 target/riscv/cpu_helper.c      |  4 +-
 4 files changed, 66 insertions(+), 34 deletions(-)

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2.31.1