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Fri, 18 Dec 2020 08:29:07 -0500 (EST) From: Klaus Jensen To: qemu-devel@nongnu.org Subject: [PATCH 0/8] hw/block/nvme: misc cmb/pmr patches Date: Fri, 18 Dec 2020 14:28:57 +0100 Message-Id: <20201218132905.967326-1-its@irrelevant.dk> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 Received-SPF: pass client-ip=64.147.123.21; envelope-from=its@irrelevant.dk; helo=wout5-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Keith Busch , Andrzej Jakowski , Stefan Hajnoczi , Klaus Jensen Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen This is a resend of "hw/block/nvme: allow cmb and pmr to coexist" with some more PMR work added (PMR RDS/WDS support). This includes a resurrection of Andrzej's series[1] from back July. Andrzej's main patch basically moved the the CMB from BAR 2 into an offset in BAR 4 (located after the MSI-X table and PBA). Having an offset on the CMB causes a bunch of calculations related to address mapping to change. So, since I couldn't get the patch to apply cleanly I took a stab at implementing the suggestion I originally came up with: simply move the MSI-X table and PBA from BAR 4 into BAR 0 (up-aligned to a 4 KiB boundary, after the main NVMe controller registers). This way we can keep the CMB at offset zero in its own BAR and free up BAR 4 for use by PMR. This makes the patch simpler and does not impact any of the existing address mapping code. Andrzej, I would prefer an Ack from you, since I pretty much voided your main patch. [1]: https://lore.kernel.org/qemu-devel/20200729220107.37758-1-andrzej.jakowski@linux.intel.com/ CC: Andrzej Jakowski Andrzej Jakowski (1): hw/block/nvme: indicate CMB support through controller capabilities register Klaus Jensen (6): hw/block/nvme: move msix table and pba to BAR 0 hw/block/nvme: allow cmb and pmr to coexist hw/block/nvme: fix controller reset/shutdown logic hw/block/nvme: rename CAP_PMR_{SHIFT,MASK} to CAP_PMRS_{SHIFT,MASK} hw/block/nvme: remove redundant zeroing of PMR registers hw/block/nvme: disable PMR at boot up Naveen Nagar (1): hw/block/nvme: add PMR RDS/WDS support hw/block/nvme.h | 2 + include/block/nvme.h | 15 ++- hw/block/nvme.c | 216 ++++++++++++++++++++++++++++++------------- 3 files changed, 164 insertions(+), 69 deletions(-)