| Message ID | 20201123065927.108923-1-its@irrelevant.dk |
|---|---|
| Headers | show |
| Series | hw/block/nvme: allow cmb and pmr to coexist | expand |
On Nov 23 07:59, Klaus Jensen wrote: > From: Klaus Jensen <k.jensen@samsung.com> > > This is a resurrection of Andrzej's series[1] from back July. > > Andrzej's main patch basically moved the the CMB from BAR 2 into an > offset in BAR 4 (located after the MSI-X table and PBA). Having an > offset on the CMB causes a bunch of calculations related to address > mapping to change. > > So, since I couldn't get the patch to apply cleanly I took a stab at > implementing the suggestion I originally came up with: simply move the > MSI-X table and PBA from BAR 4 into BAR 0 (up-aligned to a 4 KiB > boundary, after the main NVMe controller registers). This way we can > keep the CMB at offset zero in its own BAR and free up BAR 4 for use by > PMR. This makes the patch simpler and does not impact any of the > existing address mapping code. > > Andrzej, I would prefer an Ack from you, since I pretty much voided your > main patch. > > [1]: https://lore.kernel.org/qemu-devel/20200729220107.37758-1-andrzej.jakowski@linux.intel.com/ > > CC: Andrzej Jakowski <andrzej.jakowski@linux.intel.com> > > Andrzej Jakowski (1): > hw/block/nvme: indicate CMB support through controller capabilities > register > > Klaus Jensen (2): > hw/block/nvme: move msix table and pba to BAR 0 > hw/block/nvme: allow cmb and pmr to coexist > > hw/block/nvme.h | 1 + > include/block/nvme.h | 10 +++++++--- > hw/block/nvme.c | 42 +++++++++++++++++++++++++++++++----------- > 3 files changed, 39 insertions(+), 14 deletions(-) > > -- > 2.29.2 > > Gentle ping on this.
From: Klaus Jensen <k.jensen@samsung.com> This is a resurrection of Andrzej's series[1] from back July. Andrzej's main patch basically moved the the CMB from BAR 2 into an offset in BAR 4 (located after the MSI-X table and PBA). Having an offset on the CMB causes a bunch of calculations related to address mapping to change. So, since I couldn't get the patch to apply cleanly I took a stab at implementing the suggestion I originally came up with: simply move the MSI-X table and PBA from BAR 4 into BAR 0 (up-aligned to a 4 KiB boundary, after the main NVMe controller registers). This way we can keep the CMB at offset zero in its own BAR and free up BAR 4 for use by PMR. This makes the patch simpler and does not impact any of the existing address mapping code. Andrzej, I would prefer an Ack from you, since I pretty much voided your main patch. [1]: https://lore.kernel.org/qemu-devel/20200729220107.37758-1-andrzej.jakowski@linux.intel.com/ CC: Andrzej Jakowski <andrzej.jakowski@linux.intel.com> Andrzej Jakowski (1): hw/block/nvme: indicate CMB support through controller capabilities register Klaus Jensen (2): hw/block/nvme: move msix table and pba to BAR 0 hw/block/nvme: allow cmb and pmr to coexist hw/block/nvme.h | 1 + include/block/nvme.h | 10 +++++++--- hw/block/nvme.c | 42 +++++++++++++++++++++++++++++++----------- 3 files changed, 39 insertions(+), 14 deletions(-)