From patchwork Tue Feb 25 10:35:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 1243979 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=c-sky.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48Rb1j32pnz9sP7 for ; Tue, 25 Feb 2020 21:35:53 +1100 (AEDT) Received: from localhost ([::1]:52178 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6XZ9-0001B4-5s for incoming@patchwork.ozlabs.org; Tue, 25 Feb 2020 05:35:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35236) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6XYf-0001Aa-57 for qemu-devel@nongnu.org; Tue, 25 Feb 2020 05:35:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j6XYd-0001Pe-V2 for qemu-devel@nongnu.org; Tue, 25 Feb 2020 05:35:20 -0500 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:58334) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j6XYd-0001NC-Af; Tue, 25 Feb 2020 05:35:19 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.09531976|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.170054-0.0243383-0.805608; DS=CONTINUE|ham_regular_dialog|0.0116271-0.000104934-0.988268; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03267; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.GsFPuQz_1582626910; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.GsFPuQz_1582626910) by smtp.aliyun-inc.com(10.147.40.44); Tue, 25 Feb 2020 18:35:11 +0800 From: LIU Zhiwei To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Subject: [PATCH v4 0/5] target/riscv: support vector extension part 2 Date: Tue, 25 Feb 2020 18:35:03 +0800 Message-Id: <20200225103508.7651-1-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-csky@vger.kernel.org, wenmeng_zhang@c-sky.com, wxy194768@alibaba-inc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Features: * support specification riscv-v-spec-0.7.1. * support basic vector extension. * support Zvlsseg. * support Zvamo. * not support Zvediv as it is changing. * fixed SLEN 128bit. * element width support 8bit, 16bit, 32bit, 64bit. Changelog: v4 * remove check structure, use check function directly * use (s->vlen / 8) as maxsz in simd_maxsz * remove helper structure vext_ctx, pass args directly. v3 * move check code from execution time to translation time. * probe pages before real load or store access. * use probe_page_check for no-fault operations in linux user mode. * add atomic and noatomic operation for vector amo instructions. V2 * use float16_compare{_quiet} * only use GETPC() in outer most helper * add ctx.ext_v Property LIU Zhiwei (5): target/riscv: add vector unit stride load and store instructions target/riscv: add vector stride load and store instructions target/riscv: add vector index load and store instructions target/riscv: add fault-only-first unit stride load target/riscv: add vector amo operations target/riscv/helper.h | 218 ++++ target/riscv/insn32-64.decode | 11 + target/riscv/insn32.decode | 67 ++ target/riscv/insn_trans/trans_rvv.inc.c | 663 +++++++++++++ target/riscv/translate.c | 2 + target/riscv/vector_helper.c | 1203 +++++++++++++++++++++++ 6 files changed, 2164 insertions(+)