From patchwork Mon Feb 10 08:12:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 1235676 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=c-sky.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48GJZG5mnRz9sRN for ; Mon, 10 Feb 2020 19:13:25 +1100 (AEDT) Received: from localhost ([::1]:58122 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j14C3-0003r3-6D for incoming@patchwork.ozlabs.org; Mon, 10 Feb 2020 03:13:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36570) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j14Bg-0003ns-Vq for qemu-devel@nongnu.org; Mon, 10 Feb 2020 03:13:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j14Bf-0008F0-PM for qemu-devel@nongnu.org; Mon, 10 Feb 2020 03:13:00 -0500 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:46398) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j14Bf-0008Bd-A5; Mon, 10 Feb 2020 03:12:59 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.161179|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.291525-0.0425897-0.665885; DS=CONTINUE|ham_system_inform|0.0211774-0.00132143-0.977501; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03302; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=9; SR=0; TI=SMTPD_---.GmO5bfp_1581322371; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.GmO5bfp_1581322371) by smtp.aliyun-inc.com(10.147.40.44); Mon, 10 Feb 2020 16:12:51 +0800 From: LIU Zhiwei To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Subject: [PATCH v4 0/4]target-riscv: support vector extension part 1 Date: Mon, 10 Feb 2020 16:12:36 +0800 Message-Id: <20200210081240.11481-1-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This is the first part of v4 patchset. The changelog of v4 is only coverd the part1. Features: * support specification riscv-v-spec-0.7.1. * support basic vector extension. * support Zvlsseg. * support Zvamo. * not support Zvediv as it is changing. * fixed SLEN 128bit. * element width support 8bit, 16bit, 32bit, 64bit. Changelog: v4 * adjust max vlen to 512 bits. * check maximum on elen(64bits). * check minimum on vlen(128bits). * check if rs1 is x0 in vsetvl/vsetvli. * use gen_goto_tb in vsetvli instead of exit_tb. * fixup fetch vlmax from rs2, not env->vext.type. v3 * support VLEN configure from qemu command line. * support ELEN configure from qemu command line. * support vector specification version configure from qemu command line. * only default on for "any" cpu, others turn on from command line. * use a continous memory block for vector register description. V2 * use float16_compare{_quiet} * only use GETPC() in outer most helper * add ctx.ext_v Property LIU Zhiwei (4): target/riscv: add vector extension field in CPURISCVState target/riscv: configure and turn on vector extension from command line target/riscv: support vector extension csr target/riscv: add vector configure instruction MAINTAINERS | 1 + target/riscv/Makefile.objs | 2 +- target/riscv/cpu.c | 48 ++++++++++++++- target/riscv/cpu.h | 82 ++++++++++++++++++++++--- target/riscv/cpu_bits.h | 15 +++++ target/riscv/csr.c | 72 +++++++++++++++++++++- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 5 ++ target/riscv/insn_trans/trans_rvv.inc.c | 69 +++++++++++++++++++++ target/riscv/translate.c | 17 ++++- target/riscv/vector_helper.c | 49 +++++++++++++++ 11 files changed, 346 insertions(+), 16 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c create mode 100644 target/riscv/vector_helper.c