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DIR:OUT; SFP:1102; SCL:1; SRVR:DM6PR01MB5034; H:DM6PR01MB4825.prod.exchangelabs.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:0; received-spf: None (protection.outlook.com: os.amperecomputing.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: cIP+n+apadS4viL2cORlfBBfpDuXDMgkO/0yNJyb+4di2M+GAgVTvlZI8/h1m16jOMUvNTFKNjQfqTyhaI9glOjfA9LPUvg3Iwn5MlbIqg7x8rvhTBkAVkKladaxk6Tu4+e6f/ew26lSz8Jw1EuXSL3h2we+p0BGPUGmPnDvprc6wdSe1gxAGPhXahXraWoo0DGINffNZ746KlZFhYXytFFj3X70Z715lwMNUy3s6/zM2nKDszvKI9d68m8YV3ampNQqurzyhh1D3pYOUEMNBW5vUfTjH5paaUX57tBy3HjY7/3+OeWoSndWVu/8nWlv68aSnZgK8cCio9CYbfKcH/Vag/p77WcIB0sIHqwOJ7w= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: f27864d1-4c4d-4444-e889-08d6434fafbf X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Nov 2018 18:51:25.4104 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR01MB5034 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.36.123 Subject: [Qemu-devel] [PATCH v7 00/12] More fully implement ARM PMUv3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , "qemu-devel@nongnu.org" , Digant Desai Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The ARM PMU implementation currently contains a basic cycle counter, but it is often useful to gather counts of other events, filter them based on execution mode, and/or be notified on counter overflow. These patches flesh out the implementations of various PMU registers including PM[X]EVCNTR and PM[X]EVTYPER, add a struct definition to represent arbitrary counter types, implement mode filtering, send interrupts on counter overflow, and add instruction, cycle, and software increment events. Since v6 [1] I have made the following changes: * Use cpu_get_host_ticks() for the cycle counter value for user mode * Re-staged "PMU: Set PMCR.N to 4" so that the value of the pmcrn local variable matches the architectural value of PMCR.N * Re-ordered "Reorganize PMCCNTR accesses" to come first to eliminate the churn of *_op_start/finish function names and definitions * Use extract64 and ARRAY_SIZE macros where applicable * Add a return value to the post_save migration function [1] - https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg02036.html Aaron Lindsay (12): migration: Add post_save function to VMStateDescription target/arm: Reorganize PMCCNTR accesses target/arm: Swap PMU values before/after migrations target/arm: Filter cycle counter based on PMCCFILTR_EL0 target/arm: Allow AArch32 access for PMCCFILTR target/arm: Implement PMOVSSET target/arm: Add array for supported PMU events, generate PMCEID[01] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER target/arm: PMU: Add instruction and cycle events target/arm: PMU: Set PMCR.N to 4 target/arm: Implement PMSWINC target/arm: Send interrupts on PMU counter overflow docs/devel/migration.rst | 9 +- include/migration/vmstate.h | 1 + migration/vmstate.c | 13 +- target/arm/cpu.c | 28 +- target/arm/cpu.h | 68 +++- target/arm/cpu64.c | 4 - target/arm/helper.c | 774 ++++++++++++++++++++++++++++++++---- target/arm/machine.c | 20 + 8 files changed, 816 insertions(+), 101 deletions(-)