mbox series

[PULL,v2,00/25] OpenRISC updates for 3.0

Message ID 20180702151023.24532-1-shorne@gmail.com
Headers show
Series OpenRISC updates for 3.0 | expand

Message

Stafford Horne July 2, 2018, 3:09 p.m. UTC 
Hi Peter,

Changes since v1:
 - Un"fixed" an incorrect checkpatch warning pointed out by Richard.

Please consider for pull.

The following changes since commit 646f34fa5482e495483de230b4cf0f2ae4fd2781:

  tcg: Fix --disable-tcg build breakage (2018-07-02 13:42:05 +0100)

are available in the Git repository at:

  git@github.com:stffrdhrn/qemu.git tags/pull-or-20180702

for you to fetch changes up to 33e1acf437ce4f0b67c262fc93b436e2e306f278:

  target/openrisc: Fix writes to interrupt mask register (2018-07-03 00:05:28 +0900)

----------------------------------------------------------------
OpenRISC cleanups and Fixes for QEMU 3.0

Mostly patches from Richard Henderson fixing multiple things:
 * Fix singlestepping in GDB.
 * Use more TB linking.
 * Fixes to exit TB after updating SPRs to enable registering of state
   changes.
 * Significant optimizations and refactors to the TLB
 * Split out disassembly from translation.
 * Add qemu-or1k to qemu-binfmt-conf.sh.
 * Implement signal handling for linux-user.

Then there are a few fixups from me:
 * Fix delay slot detections to match hardware, this was masking a bug
   in the linus kernel.
 * Fix stores to the PIC mask register

----------------------------------------------------------------


Richard Henderson (23):
  target/openrisc: Fix mtspr shadow gprs
  target/openrisc: Add print_insn_or1k
  target/openrisc: Log interrupts
  target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP
  target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB
  target/openrisc: Fix singlestep_enabled
  target/openrisc: Link more translation blocks
  target/openrisc: Split out is_user
  target/openrisc: Exit the TB after l.mtspr
  target/openrisc: Form the spr index from tcg
  target/openrisc: Merge tlb allocation into CPUOpenRISCState
  target/openrisc: Remove indirect function calls for mmu
  target/openrisc: Merge mmu_helper.c into mmu.c
  target/openrisc: Reduce tlb to a single dimension
  target/openrisc: Fix tlb flushing in mtspr
  target/openrisc: Fix cpu_mmu_index
  target/openrisc: Use identical sizes for ITLB and DTLB
  target/openrisc: Stub out handle_mmu_fault for softmmu
  target/openrisc: Increase the TLB size
  target/openrisc: Reorg tlb lookup
  target/openrisc: Add support in scripts/qemu-binfmt-conf.sh
  linux-user: Implement signals for openrisc
  linux-user: Fix struct sigaltstack for openrisc

Stafford Horne (2):
  target/openrisc: Fix delay slot exception flag to match spec
  target/openrisc: Fix writes to interrupt mask register

 linux-user/openrisc/signal.c         | 217 ++++++++-----------
 linux-user/openrisc/target_signal.h  |   2 +-
 linux-user/openrisc/target_syscall.h |  28 +--
 linux-user/signal.c                  |   2 +-
 scripts/qemu-binfmt-conf.sh          |  10 +-
 target/openrisc/Makefile.objs        |   5 +-
 target/openrisc/cpu.c                |  17 +-
 target/openrisc/cpu.h                |  61 +++---
 target/openrisc/disas.c              | 170 +++++++++++++++
 target/openrisc/helper.h             |   4 +-
 target/openrisc/interrupt.c          |  55 +++--
 target/openrisc/interrupt_helper.c   |  35 +---
 target/openrisc/machine.c            |  44 +---
 target/openrisc/mmu.c                | 279 +++++++++---------------
 target/openrisc/mmu_helper.c         |  40 ----
 target/openrisc/sys_helper.c         |  84 ++++----
 target/openrisc/translate.c          | 303 ++++++++++-----------------
 17 files changed, 603 insertions(+), 753 deletions(-)
 create mode 100644 target/openrisc/disas.c
 delete mode 100644 target/openrisc/mmu_helper.c

Comments

Peter Maydell July 2, 2018, 3:36 p.m. UTC | #1 
On 2 July 2018 at 16:09, Stafford Horne <shorne@gmail.com> wrote:
> Hi Peter,
>
> Changes since v1:
>  - Un"fixed" an incorrect checkpatch warning pointed out by Richard.
>
> Please consider for pull.
>
> The following changes since commit 646f34fa5482e495483de230b4cf0f2ae4fd2781:
>
>   tcg: Fix --disable-tcg build breakage (2018-07-02 13:42:05 +0100)
>
> are available in the Git repository at:
>
>   git@github.com:stffrdhrn/qemu.git tags/pull-or-20180702
>
> for you to fetch changes up to 33e1acf437ce4f0b67c262fc93b436e2e306f278:
>
>   target/openrisc: Fix writes to interrupt mask register (2018-07-03 00:05:28 +0900)
>
> ----------------------------------------------------------------
> OpenRISC cleanups and Fixes for QEMU 3.0
>
> Mostly patches from Richard Henderson fixing multiple things:
>  * Fix singlestepping in GDB.
>  * Use more TB linking.
>  * Fixes to exit TB after updating SPRs to enable registering of state
>    changes.
>  * Significant optimizations and refactors to the TLB
>  * Split out disassembly from translation.
>  * Add qemu-or1k to qemu-binfmt-conf.sh.
>  * Implement signal handling for linux-user.
>
> Then there are a few fixups from me:
>  * Fix delay slot detections to match hardware, this was masking a bug
>    in the linus kernel.
>  * Fix stores to the PIC mask register
>
> ----------------------------------------------------------------

Compile failure, for the windows crossbuilds:

/home/petmay01/qemu-for-merges/target/openrisc/mmu.c: In function
'openrisc_cpu_get_phys_page_debug':
/home/petmay01/qemu-for-merges/target/openrisc/mmu.c:133:29: error:
'PROT_EXEC' undeclared (first use in this function)
                             PROT_EXEC | PROT_READ | PROT_WRITE,
                             ^
/home/petmay01/qemu-for-merges/target/openrisc/mmu.c:133:29: note:
each undeclared identifier is reported only once for each function it
appears in
/home/petmay01/qemu-for-merges/target/openrisc/mmu.c:133:41: error:
'PROT_READ' undeclared (first use in this function)
                             PROT_EXEC | PROT_READ | PROT_WRITE,
                                         ^
/home/petmay01/qemu-for-merges/target/openrisc/mmu.c:133:53: error:
'PROT_WRITE' undeclared (first use in this function)
                             PROT_EXEC | PROT_READ | PROT_WRITE,
                                                     ^
/home/petmay01/qemu-for-merges/target/openrisc/mmu.c: In function 'tlb_fill':
/home/petmay01/qemu-for-merges/target/openrisc/mmu.c:169:53: error:
'PROT_EXEC' undeclared (first use in this function)
         int need = (access_type == MMU_INST_FETCH ? PROT_EXEC
                                                     ^
/home/petmay01/qemu-for-merges/target/openrisc/mmu.c:170:55: error:
'PROT_WRITE' undeclared (first use in this function)
                     : access_type == MMU_DATA_STORE ? PROT_WRITE
                                                       ^
/home/petmay01/qemu-for-merges/target/openrisc/mmu.c:171:23: error:
'PROT_READ' undeclared (first use in this function)
                     : PROT_READ);
                       ^
/home/petmay01/qemu-for-merges/rules.mak:69: recipe for target
'target/openrisc/mmu.o' failed

PROT_READ/WRITE/EXEC are the Posix flags for mmap().
The flags for the 'prot' argument to tlb_set_page()
and similar places are PAGE_READ/WRITE/EXEC.

PS: for trivial respins of a pullreq you don't need to resend
the whole thing, you can just resend the cover letter (and
any individual patches which got major changes).

thanks
-- PMM
Stafford Horne July 3, 2018, 1:53 p.m. UTC | #2 
On Mon, Jul 02, 2018 at 04:36:10PM +0100, Peter Maydell wrote:
> On 2 July 2018 at 16:09, Stafford Horne <shorne@gmail.com> wrote:
> > Hi Peter,
> >
> > Changes since v1:
> >  - Un"fixed" an incorrect checkpatch warning pointed out by Richard.
> >
> > Please consider for pull.
> >
> > The following changes since commit 646f34fa5482e495483de230b4cf0f2ae4fd2781:
> >
> >   tcg: Fix --disable-tcg build breakage (2018-07-02 13:42:05 +0100)
> >
> > are available in the Git repository at:
> >
> >   git@github.com:stffrdhrn/qemu.git tags/pull-or-20180702
> >
> > for you to fetch changes up to 33e1acf437ce4f0b67c262fc93b436e2e306f278:
> >
> >   target/openrisc: Fix writes to interrupt mask register (2018-07-03 00:05:28 +0900)
> >
> > ----------------------------------------------------------------
> > OpenRISC cleanups and Fixes for QEMU 3.0
> >
> > Mostly patches from Richard Henderson fixing multiple things:
> >  * Fix singlestepping in GDB.
> >  * Use more TB linking.
> >  * Fixes to exit TB after updating SPRs to enable registering of state
> >    changes.
> >  * Significant optimizations and refactors to the TLB
> >  * Split out disassembly from translation.
> >  * Add qemu-or1k to qemu-binfmt-conf.sh.
> >  * Implement signal handling for linux-user.
> >
> > Then there are a few fixups from me:
> >  * Fix delay slot detections to match hardware, this was masking a bug
> >    in the linus kernel.
> >  * Fix stores to the PIC mask register
> >
> > ----------------------------------------------------------------
> 
> Compile failure, for the windows crossbuilds:
> 
[...]
> /home/petmay01/qemu-for-merges/target/openrisc/mmu.c:171:23: error:
> 'PROT_READ' undeclared (first use in this function)
>                      : PROT_READ);
>                        ^
> /home/petmay01/qemu-for-merges/rules.mak:69: recipe for target
> 'target/openrisc/mmu.o' failed
> 
> PROT_READ/WRITE/EXEC are the Posix flags for mmap().
> The flags for the 'prot' argument to tlb_set_page()
> and similar places are PAGE_READ/WRITE/EXEC.

Understood, this should be fixed now, after changing I see no differences.

> PS: for trivial respins of a pullreq you don't need to resend
> the whole thing, you can just resend the cover letter (and
> any individual patches which got major changes).

Thats good to know, I thought it might be annoying to resend the entire series
when all that is needed is the pr cover letter.

I have resent, I hope all is well.

-Stafford