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[83.254.152.225]) by smtp.gmail.com with ESMTPSA id v62sm2819800lje.39.2017.10.29.03.13.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 29 Oct 2017 03:13:46 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sun, 29 Oct 2017 11:13:30 +0100 Message-Id: <20171029101343.15544-1-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::22c Subject: [Qemu-devel] [PATCH v5 00/13] Add support for the ZynqMP Generic QSPI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Hi, This patch series is an attempt to add support for the ZynqMP QSPI (consisting of the Generic QSPI and the legacy QSPI) to the xlnx-zcu102 board and connect Numonyx n25q512a11 flashes to the QSPI. Also some functionality is added to m25p80. The series starts by adding support in m25p80 for continous read out of status registers, SST flash READ ID commands, bank address register accesses, bulk erase (0x60) and two Numonyx flashes (n25q512a11 and n25q512a13). Thereafter it updates the striping behaviour to be bit big endiann in the Xilinx QSPI model and adds support for RX discard, zero pumping according transfer register and 4 byte LQSPI addresses. Finally it adds support for the ZynqMP Generic QSPI and adds the ZynqMP QSPI to the xlnx-zcu102 board. Best regards, Francisco Iglesias Changelog: v4 -> v5 * Added newlines in patch 'xlnx-zcu102: Add support for the ZynqMP QSPI' v3 -> v4 * Corrected patch 'Add support for SST READ ID 0x90/0xAB commands' * Corrected patch 'Add support Add support for BRRD/BRWR and BULK_ERASE' * Minor tweaks in the ZynqMP GQSPI patch for reducing the patch v2 -> v3 * Tweaked commit messages * Corrected patch 08 'Make tx/rx_data_bytes more generic and reusable' * Reworked the patch adding the ZynqMP GQSPI and splitted out another QSPI related change into an own patch 'Don't set TX FIFO UNDERFLOW at cmd done' v1 -> v2 * Reset author on commits (due to mailing issues). Francisco Iglesias (13): m25p80: Add support for continuous read out of RDSR and READ_FSR m25p80: Add support for SST READ ID 0x90/0xAB commands m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60) m25p80: Add support for n25q512a11 and n25q512a13 xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass xilinx_spips: Update striping to be big-endian bit order xilinx_spips: Add support for RX discard and RX drain xilinx_spips: Make tx/rx_data_bytes more generic and reusable xilinx_spips: Add support for zero pumping xilinx_spips: Add support for 4 byte addresses in the LQSPI xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done xilinx_spips: Add support for the ZynqMP Generic QSPI xlnx-zcu102: Add support for the ZynqMP QSPI default-configs/arm-softmmu.mak | 1 + hw/arm/xlnx-zcu102.c | 23 ++ hw/arm/xlnx-zynqmp.c | 26 ++ hw/block/m25p80.c | 40 ++- hw/ssi/xilinx_spips.c | 769 +++++++++++++++++++++++++++++++++------- include/hw/arm/xlnx-zynqmp.h | 5 + include/hw/ssi/xilinx_spips.h | 71 +++- 7 files changed, 795 insertions(+), 140 deletions(-)