From patchwork Wed Nov 22 13:11:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: ~aminier X-Patchwork-Id: 1867365 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Sb1rL3j7Cz1ySX for ; Thu, 23 Nov 2023 00:12:50 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r5n0r-0006te-VJ; Wed, 22 Nov 2023 08:11:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r5n0o-0006sK-PX; Wed, 22 Nov 2023 08:11:26 -0500 Received: from mail-b.sr.ht ([173.195.146.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r5n0m-0001vc-2a; Wed, 22 Nov 2023 08:11:25 -0500 Authentication-Results: mail-b.sr.ht; dkim=none Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id DA7EF11EE04; Wed, 22 Nov 2023 13:11:19 +0000 (UTC) From: ~aminier Date: Wed, 22 Nov 2023 13:11:19 +0000 MIME-Version: 1.0 Subject: [PATCH qemu v2 0/1] Implement STM32L4x5 EXTI Message-ID: <170065867969.8823.8108107963720785285-0@git.sr.ht> X-Mailer: git.sr.ht To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, alistair@alistair23.me, philmd@linaro.org, peter.maydell@linaro.org, ines.varhol@telecom-paris.fr, arnaud.minier@telecom-paris.fr Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~aminier Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch allows to emulate the STM32L4x5 EXTI device. It implements register access and software interruptions. This is RFC since we still have troubles to make all tests pass. More precisely, the line `g_assert_true(get_irq(GPIO_0_IRQ));` fails in the software interrupts test. No irq seems to be fired. (We also tested the stm32f4_exti (on which this implementation is based upon) on but it also fails so don't really know if the test or the implementation is incorrect). Thank you Philippe for your reviews ! They are really useful ! The code is now more concise and clear. Also, Inès and I were wondering what would be the next step for our previous patchset that adds support for the B-L475E-IOT01A board and STM32L4x5 SoC. We used the RFC tag because we were unsure if this met Qemu quality standard. But now that this has been reviewed, is there anything we should to move it forward and merge it ? Sincerely, Arnaud Minier Changes from v1 to v2: - use arrays to deduplicate code and logic - move internal constant `EXTI_NUM_GPIO_EVENT_IN_LINES` from the header to the .c file - Improve copyright headers - replace `static const` with `#define` - use the DEFINE_TYPES macro - fill the `impl` and `valid` field of the exti's `MemoryRegionOps` - fix invalid test caused by a last minute change Based-on: <170049810484.22920.612074576971878323-0@git.sr.ht> ([RFC v3 2/2] hw/arm: Add minimal support for the B-L475E-IOT01A board) Arnaud Minier (1): Implement STM32L4x5 EXTI hw/arm/Kconfig | 1 + hw/arm/stm32l4x5_soc.c | 65 ++++++- hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/misc/stm32l4x5_exti.c | 303 ++++++++++++++++++++++++++++++ hw/misc/trace-events | 5 + include/hw/arm/stm32l4x5_soc.h | 3 + include/hw/misc/stm32l4x5_exti.h | 58 ++++++ tests/qtest/meson.build | 5 + tests/qtest/stm32l4x5_exti-test.c | 104 ++++++++++ 10 files changed, 546 insertions(+), 2 deletions(-) create mode 100644 hw/misc/stm32l4x5_exti.c create mode 100644 include/hw/misc/stm32l4x5_exti.h create mode 100644 tests/qtest/stm32l4x5_exti-test.c