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[v3,0/5] Add Icelake CPU model

Message ID 1530695199-27601-1-git-send-email-robert.hu@linux.intel.com
Headers show
Series Add Icelake CPU model | expand

Message

Robert Hoo July 4, 2018, 9:06 a.m. UTC 
This patch set defines the new guest CPU models of Icelake.

The first patch defines new indices for IA32_PRED_CMD MSR (IBPB) and IA32_ARCH_CAPABILITIES MSR.
Other patches add CPUID bits feature words for new features, like PCONFIG,
WBNOINVD. The final patch defines Icelake-{Server,Client} CPU models.

Changelog:
v3
	Remove ARCH_CAPABILITIES from Icelake CPU model, at present. Going to
compose a separate patch to do 1) qemu set ARCH_CAPABILITES MSR with some default
value. 2) expand current CPU feature expression frame work from CPUID features
only to MSR bit included as well.
	Fix some patch format error and update some trivial patch descrptions.
v2
	Per Paolo's comment, remove unnecessary CPU vmstate check for write/read only
IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs.

Robert Hoo (5):
  i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES
  i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR
  i386: Add CPUID bit for PCONFIG
  i386: Add CPUID bit for WBNOINVD
  i386: Add new CPU model Icelake-{Server,Client}

 target/i386/cpu.c | 121 ++++++++++++++++++++++++++++++++++++++++++++++++++++--
 target/i386/cpu.h |   6 +++
 2 files changed, 124 insertions(+), 3 deletions(-)