@@ -139,6 +139,7 @@ config RESET_MESON_AUDIO_ARB
config RESET_NPCM
bool "NPCM BMC Reset Driver" if COMPILE_TEST
default ARCH_NPCM
+ select AUXILIARY_BUS
help
This enables the reset controller driver for Nuvoton NPCM
BMC SoCs.
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2019 Nuvoton Technology corporation.
+#include <linux/auxiliary_bus.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
@@ -10,11 +11,14 @@
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/reset-controller.h>
+#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <linux/of_address.h>
+#include <soc/nuvoton/clock-npcm8xx.h>
+
/* NPCM7xx GCR registers */
#define NPCM_MDLR_OFFSET 0x7C
#define NPCM7XX_MDLR_USBD0 BIT(9)
@@ -89,6 +93,7 @@ struct npcm_rc_data {
const struct npcm_reset_info *info;
struct regmap *gcr_regmap;
u32 sw_reset_number;
+ struct device *dev;
void __iomem *base;
spinlock_t lock;
};
@@ -373,6 +378,67 @@ static const struct reset_control_ops npcm_rc_ops = {
.status = npcm_rc_status,
};
+static void npcm_clock_unregister_adev(void *_adev)
+{
+ struct auxiliary_device *adev = _adev;
+
+ auxiliary_device_delete(adev);
+ auxiliary_device_uninit(adev);
+}
+
+static void npcm_clock_adev_release(struct device *dev)
+{
+ struct auxiliary_device *adev = to_auxiliary_dev(dev);
+ struct npcm_clock_adev *rdev = to_npcm_clock_adev(adev);
+
+ kfree(rdev);
+}
+
+static struct auxiliary_device *npcm_clock_adev_alloc(struct npcm_rc_data *rst_data, char *clk_name)
+{
+ struct npcm_clock_adev *rdev;
+ struct auxiliary_device *adev;
+ int ret;
+
+ rdev = kzalloc(sizeof(*rdev), GFP_KERNEL);
+ if (!rdev)
+ return ERR_PTR(-ENOMEM);
+
+ rdev->base = rst_data->base;
+
+ adev = &rdev->adev;
+ adev->name = clk_name;
+ adev->dev.parent = rst_data->dev;
+ adev->dev.release = npcm_clock_adev_release;
+ adev->id = 555u;
+
+ ret = auxiliary_device_init(adev);
+ if (ret) {
+ kfree(rdev);
+ return ERR_PTR(ret);
+ }
+
+ return adev;
+}
+
+static int npcm8xx_clock_controller_register(struct npcm_rc_data *rst_data, char *clk_name)
+{
+ struct auxiliary_device *adev;
+ int ret;
+
+ adev = npcm_clock_adev_alloc(rst_data, clk_name);
+ if (IS_ERR(adev))
+ return PTR_ERR(adev);
+
+ ret = auxiliary_device_add(adev);
+ if (ret) {
+ auxiliary_device_uninit(adev);
+ return ret;
+ }
+
+ return devm_add_action_or_reset(rst_data->dev, npcm_clock_unregister_adev, adev);
+}
+
static int npcm_rc_probe(struct platform_device *pdev)
{
struct npcm_rc_data *rc;
@@ -393,6 +459,7 @@ static int npcm_rc_probe(struct platform_device *pdev)
rc->rcdev.of_node = pdev->dev.of_node;
rc->rcdev.of_reset_n_cells = 2;
rc->rcdev.of_xlate = npcm_reset_xlate;
+ rc->dev = &pdev->dev;
ret = devm_reset_controller_register(&pdev->dev, &rc->rcdev);
if (ret) {
@@ -414,7 +481,12 @@ static int npcm_rc_probe(struct platform_device *pdev)
}
}
- return ret;
+ switch (rc->info->bmc_id) {
+ case BMC_NPCM8XX:
+ return npcm8xx_clock_controller_register(rc, "clk-npcm8xx");
+ default:
+ return ret;
+ }
}
static struct platform_driver npcm_rc_driver = {
new file mode 100644
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __SOC_NPCM8XX_CLOCK_H
+#define __SOC_NPCM8XX_CLOCK_H
+
+#include <linux/auxiliary_bus.h>
+#include <linux/container_of.h>
+
+struct npcm_clock_adev {
+ void __iomem *base;
+ struct auxiliary_device adev;
+};
+
+#define to_npcm_clock_adev(_adev) \
+ container_of((_adev), struct npcm_clock_adev, adev)
+
+#endif