From patchwork Fri Oct 2 21:37:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Denis Kirjanov X-Patchwork-Id: 525819 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 1913B1402F0 for ; Sat, 3 Oct 2015 07:38:41 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id CE2A81A0701 for ; Sat, 3 Oct 2015 07:38:40 +1000 (AEST) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from mail-yk0-f176.google.com (mail-yk0-f176.google.com [209.85.160.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 27D091A0035 for ; Sat, 3 Oct 2015 07:37:38 +1000 (AEST) Received: by ykdz138 with SMTP id z138so123117462ykd.2 for ; Fri, 02 Oct 2015 14:37:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=yQ4DTcELKXaB7Sy0v+vFgg22yMMcGC2DAQn9EEEZW70=; b=g8Vj0fT+J04PC4HzTIK+14dvW31HH0PMQXRqYD/sOTwKplbVPPJMCYTfChQMbuVOuS nL1qgdt408bjzIwkX5dIivzHHayWZHe1CtACKWTyd5sTfsJymsAgOglOVWBaguhEIQ/8 Sa8fpf1mvV5Ns2DtBJ53jDah6Tl6FQabuksu7HdSwxLDzcRyAq2cmbzymgJxUsSY4Sdc Cwk5J1j0q1gAtg1uqxSXfXdi4rWVDMoX4hK4Az1dIOs3KBPAbQtUFQojbHdvcXr2bZK5 2PXrQx74YUOL+KIZZ1mhqPLWaUWWnr4KmrGItwb4NsfWvf2rOu7MAcd9Oohl85xkdJ5G s5EQ== X-Gm-Message-State: ALoCoQnK/yWRlwJ00mzK0qxknbE8j5Vq93aSgexXBgsptKwViv3iqxhNMpXUhDEZmlPRTxVU+XcT MIME-Version: 1.0 X-Received: by 10.129.111.6 with SMTP id k6mr15420458ywc.114.1443821855859; Fri, 02 Oct 2015 14:37:35 -0700 (PDT) Received: by 10.37.21.134 with HTTP; Fri, 2 Oct 2015 14:37:35 -0700 (PDT) X-Originating-IP: [5.35.73.89] In-Reply-To: <1443816930.13186.214.camel@otta> References: <560EA623.1040300@redhat.com> <1443816930.13186.214.camel@otta> Date: Sat, 3 Oct 2015 00:37:35 +0300 Message-ID: Subject: Re: Missing operand for tlbie instruction on Power7 From: Denis Kirjanov To: Peter Bergner X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "linuxppc-dev@lists.ozlabs.org" , Laura Abbott , Paul Mackerras , Linux Kernel Mailing List Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 10/2/15, Peter Bergner wrote: > On Fri, 2015-10-02 at 22:03 +0300, Denis Kirjanov wrote: >> arch/powerpc/kernel/swsusp_asm64.S: Assembler messages: >>> arch/powerpc/kernel/swsusp_asm64.S:188: Error: missing operand >>> scripts/Makefile.build:294: recipe for target >>> 'arch/powerpc/kernel/swsusp_asm64.o' failed >>> make[1]: *** [arch/powerpc/kernel/swsusp_asm64.o] Error 1 >>> Makefile:941: recipe for target 'arch/powerpc/kernel' failed >>> make: *** [arch/powerpc/kernel] Error 2 > [snip] >>> I don't know enough ppc assembly to properly fix this but I can test. >> >> Could you please test the patch attached? > [snip] >> -0: tlbie r4; \ >> +0: tlbie r4, 0; \ > > This isn't correct. With POWER7 and later (which this compile > is, since it's on LE), the tlbie instruction takes two register > operands: > > tlbie RB, RS > > The tlbie instruction on pre POWER7 cpus had one required register > operand (RB) and an optional second L operand, where if you omitted > it, it was the same as using "0": > > tlbie RB, L > > This is a POWER7 and later build, so your change which adds the "0" > above is really adding r0 for RS. The new tlbie instruction doesn't > treat r0 specially, so you'll be using whatever random bits which > happen to be in r0 which I don't think that is what you want. Ok, than we can just zero out r5 for example and use it in tlbie as RS, right? > > > Peter > > > > diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h index dd0fc18..cb0f627 100644 --- a/arch/powerpc/include/asm/ppc_asm.h +++ b/arch/powerpc/include/asm/ppc_asm.h @@ -443,9 +443,10 @@ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,945) #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx) #define tlbia \ li r4,1024; \ + li r5,0; \ mtctr r4; \ lis r4,KERNELBASE@h; \ -0: tlbie r4; \ +0: tlbie r4, r5; \ addi r4,r4,0x1000; \ bdnz 0b #endif