From patchwork Sun Jan 23 13:43:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike X-Patchwork-Id: 1583112 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=RPz+WJkG; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JhWQx2vT4z9t6g for ; Sun, 23 Jan 2022 22:41:13 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4JhWQs4qq9z3bT0 for ; Sun, 23 Jan 2022 22:41:09 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=RPz+WJkG; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::a32; helo=mail-vk1-xa32.google.com; envelope-from=michael.heltne@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=RPz+WJkG; dkim-atps=neutral Received: from mail-vk1-xa32.google.com (mail-vk1-xa32.google.com [IPv6:2607:f8b0:4864:20::a32]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4JhWQZ6wSlz2yJw for ; Sun, 23 Jan 2022 22:40:52 +1100 (AEDT) Received: by mail-vk1-xa32.google.com with SMTP id n14so8350922vkk.6 for ; Sun, 23 Jan 2022 03:40:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:from:date:message-id:subject:to; bh=UR2PutA/Mk32cpXxf1FEEwnFGdZdXv0lk9d2O3MzX9U=; b=RPz+WJkGnFa+tIu0KocDsLMH3mVshC20FQqgilb2GNSP7SduFXVvAllJXQFHVCk9Gz SnzlpIhdj/+E+wIVhEI8e7vKouifznlblwksupn3AFNasuV1wfclJHHEPrQTV5S07pJm e3mlATEOaTcJSp50IIzOBk9NExepgMFz6/142xFktzUxhP8L5ODHrGeHREYDTG5WbMP/ 4YrtYckuh6DUGO2J3sgVBshmktLGSoQM0DnZonw4t5Cp+IzCLsMUebgnpuEuyEutUD8t KY2CtuNPxFszaK2t3i7ODfYlG4k2GKq8Tp4gQqOMQwviyDLHEM1Cy88alByh3HEHqNla zHLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=UR2PutA/Mk32cpXxf1FEEwnFGdZdXv0lk9d2O3MzX9U=; b=YX1mzyJj77Xm6pKZR/mU/5i4MAOD0Jy9YgQmjgOojuMfQAXdFLYZwIeDDmtOAErG4f HqLVzlidvj9BQ3j9nUgRi91+QB+4Toq2n2oEmDBLpHiWtjIr1jfJ7Pgix7dMuN3+NbWg GLZwIx/gtmPKigFJFiHKTWZ2OsR2grOFZLU7MisFhaPooo1CNXCERVZM4TnxOy+9I3x5 x5pDqT7ny2KhHls1iIYE9ONlBn6OmjbrE+uoDNh6Eeuw2H4gm8Y+D5UtEuXEbuBwAHXn 8fJeOMQXabgob/+GeG1sIfeTl4g64FtUI43TSOipRytRYPfpfBxIQ2SrwhIiTFrQkRff SECA== X-Gm-Message-State: AOAM530mqdFYMub8gIREUg0oA5rnroi3Y/0LBvGEg5PYLWYjgASy2720 U/BU3yTfouAmW905Z2Sx6bkCADIq0I7gekFXWa9T8Ryhz0uZIQ== X-Google-Smtp-Source: ABdhPJwBsMFPLKHnRqolNhU2kuKyXDhhiQNVVNXNf1OzbOi8oPcPztD2B6WaJX8OQqpZjEFa1VXQd8ZeBAbYnLCMDAo= X-Received: by 2002:a1f:948f:: with SMTP id w137mr4374412vkd.0.1642938048804; Sun, 23 Jan 2022 03:40:48 -0800 (PST) MIME-Version: 1.0 From: Mike Date: Sun, 23 Jan 2022 14:43:22 +0100 Message-ID: Subject: [PATCH] powerpc: fix building after binutils changes. To: "open list:LINUX FOR POWERPC..." X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" As some have probably noticed, we are seeing errors like ' Error: unrecognized opcode: `ptesync'' 'dssall' and 'stbcix' as a result of binutils changes, making compiling all that more fun again. The only question on my mind still is this: ---- return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr); @@ -352,7 +352,8 @@ static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr) __raw_writeq((__force unsigned long)cpu_to_be64(v), addr); } #define __raw_writeq_be __raw_writeq_be - +#endif +#ifdef CONFIG_POWER6_CPU /* * Real mode versions of the above. Those instructions are only supposed * to be used in hypervisor real mode as per the architecture spec. @@ -417,7 +418,7 @@ static inline u64 __raw_rm_readq(volatile void __iomem *paddr) : "=r" (ret) : "r" (paddr) : "memory"); return ret; } -#endif /* __powerpc64__ */ +#endif /* CONFIG_POWER6_CPU */ --- Will there come a mail saying this broke the PPC6'ish based CPU someone made in their garage? And lwesync is a valid PPC32 instruction, should i just follow the example above where BARRIER_LWESYNC is PPC64 only? https://github.com/threader/linux/commits/master-build-ppc - linux-next Best regards. Michael Heltne From 226efa05733457bb5c483f30aab6d5c6a304422c Mon Sep 17 00:00:00 2001 From: threader Date: Sun, 23 Jan 2022 14:17:10 +0100 Subject: [PATCH] arch: powerpc: fix building after binutils changes. 'dssall' in mmu_context.c is an altivec instruction, build that accordingly. 'ptesync' is a PPC64 instruction, so dont go there for if not. And apparently ifdef __powerpc64__ isnt enough in all configurations and 'stbcix' and friends, all POWER6 instructions hopefully not needed by CONFIG_PPC64 in general, wanted to play. Signed-off-by: Micahel B Heltne --- arch/powerpc/include/asm/io.h | 7 ++++--- arch/powerpc/lib/sstep.c | 4 +++- arch/powerpc/mm/Makefile | 3 +++ arch/powerpc/mm/pageattr.c | 4 ++-- 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h index beba4979bff939..d3a9c91cd06a8b 100644 --- a/arch/powerpc/include/asm/io.h +++ b/arch/powerpc/include/asm/io.h @@ -334,7 +334,7 @@ static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) } #define __raw_writel __raw_writel -#ifdef __powerpc64__ +#ifdef CONFIG_PPC64 static inline unsigned long __raw_readq(const volatile void __iomem *addr) { return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr); @@ -352,7 +352,8 @@ static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr) __raw_writeq((__force unsigned long)cpu_to_be64(v), addr); } #define __raw_writeq_be __raw_writeq_be - +#endif +#ifdef CONFIG_POWER6_CPU /* * Real mode versions of the above. Those instructions are only supposed * to be used in hypervisor real mode as per the architecture spec. @@ -417,7 +418,7 @@ static inline u64 __raw_rm_readq(volatile void __iomem *paddr) : "=r" (ret) : "r" (paddr) : "memory"); return ret; } -#endif /* __powerpc64__ */ +#endif /* CONFIG_POWER6_CPU */ /* * diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c index a94b0cd0bdc5ca..4ffd6791b03ec0 100644 --- a/arch/powerpc/lib/sstep.c +++ b/arch/powerpc/lib/sstep.c @@ -1465,7 +1465,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, switch ((word >> 1) & 0x3ff) { case 598: /* sync */ op->type = BARRIER + BARRIER_SYNC; -#ifdef __powerpc64__ +#ifdef CONFIG_PPC64 switch ((word >> 21) & 3) { case 1: /* lwsync */ op->type = BARRIER + BARRIER_LWSYNC; @@ -3267,9 +3267,11 @@ void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op) case BARRIER_LWSYNC: asm volatile("lwsync" : : : "memory"); break; +#ifdef CONFIG_PPC64 case BARRIER_PTESYNC: asm volatile("ptesync" : : : "memory"); break; +#endif } break; diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile index df8172da2301b7..2f87e77315997a 100644 --- a/arch/powerpc/mm/Makefile +++ b/arch/powerpc/mm/Makefile @@ -4,6 +4,9 @@ # ccflags-$(CONFIG_PPC64) := $(NO_MINIMAL_TOC) +ifeq ($(CONFIG_ALTIVEC),y) +CFLAGS_mmu_context.o += $(call cc-option, -maltivec, -mabi=altivec) +endif obj-y := fault.o mem.o pgtable.o mmap.o maccess.o pageattr.o \ init_$(BITS).o pgtable_$(BITS).o \ diff --git a/arch/powerpc/mm/pageattr.c b/arch/powerpc/mm/pageattr.c index edea388e9d3fbb..ccd04a386e28fc 100644 --- a/arch/powerpc/mm/pageattr.c +++ b/arch/powerpc/mm/pageattr.c @@ -54,11 +54,11 @@ static int change_page_attr(pte_t *ptep, unsigned long addr, void *data) } pte_update(&init_mm, addr, ptep, ~0UL, pte_val(pte), 0); - +#ifdef CONFIG_PPC64 /* See ptesync comment in radix__set_pte_at() */ if (radix_enabled()) asm volatile("ptesync": : :"memory"); - +#endif flush_tlb_kernel_range(addr, addr + PAGE_SIZE); spin_unlock(&init_mm.page_table_lock);