From patchwork Thu Apr 21 16:00:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Dufour X-Patchwork-Id: 613182 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qrNyx5M2Sz9sDk for ; Fri, 22 Apr 2016 02:11:05 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3qrNyx4btmzDqmG for ; Fri, 22 Apr 2016 02:11:05 +1000 (AEST) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from ozlabs.org (ozlabs.org [103.22.144.67]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3qrNxn55mzzDq6B for ; Fri, 22 Apr 2016 02:10:05 +1000 (AEST) Received: by ozlabs.org (Postfix) id 3qrNxn35d7z9sdQ; Fri, 22 Apr 2016 02:10:05 +1000 (AEST) Delivered-To: linuxppc-dev@ozlabs.org Received: from e06smtp07.uk.ibm.com (e06smtp07.uk.ibm.com [195.75.94.103]) (using TLSv1.2 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qrNxm2q7Cz9sDk for ; Fri, 22 Apr 2016 02:10:04 +1000 (AEST) Received: from localhost by e06smtp07.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 21 Apr 2016 17:09:59 +0100 X-IBM-Helo: d06dlp02.portsmouth.uk.ibm.com X-IBM-MailFrom: ldufour@linux.vnet.ibm.com X-IBM-RcptTo: linuxppc-dev@ozlabs.org Received: from b06cxnps3074.portsmouth.uk.ibm.com (d06relay09.portsmouth.uk.ibm.com [9.149.109.194]) by d06dlp02.portsmouth.uk.ibm.com (Postfix) with ESMTP id 5D4AA219007A for ; Thu, 21 Apr 2016 16:59:46 +0100 (BST) Received: from d06av04.portsmouth.uk.ibm.com (d06av04.portsmouth.uk.ibm.com [9.149.37.216]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u3LG08hj5046550 for ; Thu, 21 Apr 2016 16:00:08 GMT Received: from d06av04.portsmouth.uk.ibm.com (localhost [127.0.0.1]) by d06av04.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u3LG04QF011779 for ; Thu, 21 Apr 2016 10:00:08 -0600 Received: from [9.164.128.247] (icon-9-164-128-247.megacenter.de.ibm.com [9.164.128.247]) by d06av04.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id u3LG01B9011437; Thu, 21 Apr 2016 10:00:02 -0600 Subject: Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes To: Michael Ellerman , Anshuman Khandual , linux-kernel@vger.kernel.org, linuxppc-dev@ozlabs.org References: <1455613198-5113-1-git-send-email-khandual@linux.vnet.ibm.com> <57062722.5090706@linux.vnet.ibm.com> <5EA48413-85A1-4CB7-8843-CE22B2BB1F08@ellerman.id.au> <570B54EB.90507@linux.vnet.ibm.com> <1460524468.30704.5.camel@ellerman.id.au> From: Laurent Dufour Message-ID: <5718F901.6010104@linux.vnet.ibm.com> Date: Thu, 21 Apr 2016 18:00:01 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: <1460524468.30704.5.camel@ellerman.id.au> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16042116-0029-0000-0000-000013E60C57 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mikey@neuling.org, james.hogan@imgtec.com, avagin@openvz.org, Paul.Clothier@imgtec.com, peterz@infradead.org, palves@redhat.com, emachado@linux.vnet.ibm.com, shuahkh@osg.samsung.com, akpm@linux-foundation.org, oleg@redhat.com, dhowells@redhat.com, Ulrich.Weigand@de.ibm.com, kirjanov@gmail.com, davej@redhat.com, tglx@linutronix.de, sukadev@linux.vnet.ibm.com, davem@davemloft.net, sam.bobroff@au1.ibm.com Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 13/04/2016 07:14, Michael Ellerman wrote: > On Mon, 2016-04-11 at 09:40 +0200, Laurent Dufour wrote: >> On 07/04/2016 23:49, Michael Ellerman wrote: >>> On 7 April 2016 7:23:46 pm AEST, Laurent Dufour wrote: >>>> This series is required to handle TM state in CRIU. >>>> Is there a chance to get it upstream soon ? >>> >>> We were waiting on the gdb support to make sure it had some testing. If it's working for CRIU that would be a good data point, have you actually tested it with CRIU? >> >> I just started integrating it in CRIU, my basic tests didn't report any >> issue with the new ptrace API, but I can't state that it is bug free ;) > > Sure. But if it's working for CRIU that's at least postive :) I did additional tests and the Anshuman's series is working fine for CRIU's support with the attached patch applied. Michael, could you please applied the attached patch among the Anshuman's series ? Thanks, Laurent. From 7a4f07c54afdbe7bef84d1f700ab9262f449513a Mon Sep 17 00:00:00 2001 From: Laurent Dufour Date: Mon, 11 Apr 2016 18:59:16 +0200 Subject: [PATCH] ppc64: allow ptrace to set TM bits This patch allows the MSR bits relative to the Transactional memory state to be manipulated through the ptrace API. However, in the case the TM available bit is not set in the manipulated MSR, the changes are ignored. When dealing with the checkpointed MSR, we must be sure that the TM state bits will not be set since the checkpointed state can't be a transactional one. Signed-off-by: Laurent Dufour --- arch/powerpc/kernel/ptrace.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c index b063fc499c1d..5c792f0bf1ca 100644 --- a/arch/powerpc/kernel/ptrace.c +++ b/arch/powerpc/kernel/ptrace.c @@ -161,8 +161,12 @@ const char *regs_query_register_name(unsigned int offset) #ifdef CONFIG_PPC_ADV_DEBUG_REGS #define MSR_DEBUGCHANGE 0 #else +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM +#define MSR_DEBUGCHANGE (MSR_TS_MASK | MSR_SE | MSR_BE) +#else #define MSR_DEBUGCHANGE (MSR_SE | MSR_BE) #endif +#endif /* * Max register writeable via put_reg @@ -180,6 +184,12 @@ static unsigned long get_user_msr(struct task_struct *task) static int set_user_msr(struct task_struct *task, unsigned long msr) { +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + if (!(task->thread.regs->msr & MSR_TM)) { + /* If TM is not available, discard TM bits changes */ + msr &= ~(MSR_TM | MSR_TS_MASK); + } +#endif task->thread.regs->msr &= ~MSR_DEBUGCHANGE; task->thread.regs->msr |= msr & MSR_DEBUGCHANGE; return 0; @@ -193,6 +203,7 @@ static unsigned long get_user_ckpt_msr(struct task_struct *task) static int set_user_ckpt_msr(struct task_struct *task, unsigned long msr) { + msr &= ~MSR_TS_MASK; /* Checkpoint state can't be in transaction */ task->thread.ckpt_regs.msr &= ~MSR_DEBUGCHANGE; task->thread.ckpt_regs.msr |= msr & MSR_DEBUGCHANGE; return 0; -- 1.9.1