From patchwork Wed Jun 16 15:12:42 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Micha Nelissen X-Patchwork-Id: 55894 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from bilbo.ozlabs.org (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id 336511009CA for ; Thu, 17 Jun 2010 01:15:26 +1000 (EST) Received: from edu-smtp-01.edutel.nl (edu-smtp-01.edutel.nl [88.159.1.175]) by ozlabs.org (Postfix) with ESMTP id B039D1007D2 for ; Thu, 17 Jun 2010 01:15:08 +1000 (EST) Received: from neli.hopto.org (98-215.ftth.onsbrabantnet.nl [88.159.215.98]) by edu-smtp-01.edutel.nl (Postfix) with ESMTPSA id BD36A38610; Wed, 16 Jun 2010 17:15:06 +0200 (CEST) Received: from localhost ([127.0.0.1] ident=micha) by neli.hopto.org with esmtp (Exim 4.69) (envelope-from ) id 1OOuKW-0006RJ-SR; Wed, 16 Jun 2010 17:15:04 +0200 Message-ID: <4C18E9EA.2090903@neli.hopto.org> Date: Wed, 16 Jun 2010 17:12:42 +0200 From: Micha Nelissen User-Agent: Thunderbird 2.0.0.5 (Windows/20070716) MIME-Version: 1.0 To: Kumar Gala Subject: Re: [PATCH] e500v2 36 bit large physical HID0[EN_MAS7_UPDATE] References: <4C187616.4000303@neli.hopto.org> In-Reply-To: Cc: linuxppc-dev@lists.ozlabs.org X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Kumar Gala wrote: >> +BEGIN_MMU_FTR_SECTION >> + mfspr r2,SPRN_HID0 >> + ori r2,r2,HID0_EN_MAS7_UPDATE@l >> + mtspr SPRN_HID0, r2 >> +END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS) >> +#endif > > If you want to do this, do it in: > > arch/powerpc/kernel/cpu_setup_fsl_booke.S Do you mean like attached? I had to change the order of the '_GLOBAL' definitions __setup_cpu_e500v1/__setup_cpu_e500v2 since this bit is e500v2 only. Thanks, Micha Index: linux/arch/powerpc/kernel/cpu_setup_fsl_booke.S =================================================================== --- linux/arch/powerpc/kernel/cpu_setup_fsl_booke.S (revision 2871) +++ linux/arch/powerpc/kernel/cpu_setup_fsl_booke.S (working copy) @@ -57,8 +57,14 @@ ori r3,r3,HID0_DAPUEN@l mtspr SPRN_HID0,r3 b __setup_e200_ivors +_GLOBAL(__setup_cpu_e500v2) +#ifdef CONFIG_PTE_64BIT + /* enable mas7 register for tlbre/tlbsx */ + mfspr r2,SPRN_HID0 + ori r2,r2,HID0_EN_MAS7_UPDATE@l + mtspr SPRN_HID0,r2 +#endif _GLOBAL(__setup_cpu_e500v1) -_GLOBAL(__setup_cpu_e500v2) mflr r4 bl __e500_icache_setup bl __e500_dcache_setup Index: linux/arch/powerpc/include/asm/reg.h =================================================================== --- linux/arch/powerpc/include/asm/reg.h (revision 2871) +++ linux/arch/powerpc/include/asm/reg.h (working copy) @@ -276,6 +276,7 @@ #define HID0_DAPUEN (1<<8) /* Debug APU enable */ #define HID0_SGE (1<<7) /* Store Gathering Enable */ #define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ +#define HID0_EN_MAS7_UPDATE (1<<7) /* Enable MAS7 reg for tlbre/tlbsx */ #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ #define HID0_LRSTK (1<<4) /* Link register stack - 745x */ #define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */