From patchwork Mon Nov 3 19:32:55 2008 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmVuw6kgQsO8cmdlbA==?= X-Patchwork-Id: 6955 X-Patchwork-Delegate: grant.likely@secretlab.ca Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id 1DF2D47508 for ; Tue, 4 Nov 2008 06:32:49 +1100 (EST) X-Original-To: linuxppc-dev@ozlabs.org Delivered-To: linuxppc-dev@ozlabs.org Received: from mo-p00-ob.rzone.de (mo-p00-ob.rzone.de [81.169.146.160]) by ozlabs.org (Postfix) with ESMTP id 6D6E5DDEDE for ; Tue, 4 Nov 2008 06:32:14 +1100 (EST) X-RZG-CLASS-ID: mo00 X-RZG-AUTH: :O2kGeEG7b/pS1Fi3Qny8h5cV9+njuawu84na/cL5YoHgc/7iwRiKVLzvXfs3/QW1 Received: from obelix.unicontrol.de (pd907c61f.dip0.t-ipconnect.de [217.7.198.31]) by post.webmailer.de (klopstock mo20) (RZmta 17.14) with ESMTP id z040b6kA3JHwZX ; Mon, 3 Nov 2008 20:32:11 +0100 (MET) (envelope-from: ) Received: from localhost (localhost [127.0.0.1]) by obelix.unicontrol.de (Postfix on SuSE Linux 8.1 (i386)) with ESMTP id 3772D17DFC; Mon, 3 Nov 2008 20:31:48 +0100 (CET) Received: from [192.168.1.55] (arkturus.unicontrol.de [192.168.1.55]) by obelix.unicontrol.de (Postfix on SuSE Linux 8.1 (i386)) with ESMTP id 4EA2817DFB; Mon, 3 Nov 2008 20:31:44 +0100 (CET) Message-ID: <490F51E7.3020309@unicontrol.de> Date: Mon, 03 Nov 2008 20:32:55 +0100 From: =?ISO-8859-15?Q?Ren=E9_B=FCrgel?= User-Agent: Thunderbird 2.0.0.17 (X11/20080930) MIME-Version: 1.0 To: linuxppc-dev@ozlabs.org Subject: [PATCH] workaround for mpc52xx erratum #364 (serial may not be reset in break state) X-Virus-Scanned: by AMaViS 0.3.12pre8 X-BeenThere: linuxppc-dev@ozlabs.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org Hi This patch is a workaround for bug #364 found in the MPC52xx processor. The errata document can be found under http://www.freescale.com/files/32bit/doc/errata/MPC5200E.pdf?fpsp=1&WT_TYPE=Errata&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation When a device with a low baudrate is connected to the serial port, but the processor "listens" on a higher baudrate, it might falsely receive breaks from the controller. During a break, the serial controller may not be reset. The appended patch provides a workaround for that situation by lowering the baudrate without resetting the controller and waiting until no break is received anymore. diff --git a/drivers/serial/mpc52xx_uart.c b/drivers/serial/mpc52xx_uart.c index 6117d3d..929524b 100644 --- a/drivers/serial/mpc52xx_uart.c +++ b/drivers/serial/mpc52xx_uart.c @@ -496,6 +496,27 @@ mpc52xx_uart_break_ctl(struct uart_port *port, int ctl) spin_unlock_irqrestore(&port->lock, flags); } +/* macro with helper macros to safely reset rx which mustn't be done in break state. + * This is a workaround for processor bug #364 described in MPC5200 (L25R) Errata. + * + * The workaround resets the baudrate to 4800, waits for a stable state and resets break state repeatedly if necessary + * optionally it can release the lock while waiting. + * 1 character at 4800 baud takes 2ms, 3ms should be enough for 1 character at higher speed and 1 char at lowest + * works only with longer delays + */ +#define LOCK(code) code +#define DONT_LOCK(code) +#define mpc52xx_uart_reset_rx(LOCK) \ + out_8(&psc->ctur,0x01); \ + out_8(&psc->ctlr,0xae); \ + do { \ + out_8(&psc->command,MPC52xx_PSC_RST_ERR_STAT); \ + LOCK(disable_irq(port->irq); spin_unlock_irqrestore(&port->lock, flags)); \ + mdelay(10); \ + LOCK(spin_lock_irqsave(&port->lock, flags); enable_irq(port->irq)); \ + } while ((in_be16(&psc->mpc52xx_psc_status)) & MPC52xx_PSC_SR_RB); \ + out_8(&psc->command,MPC52xx_PSC_RST_RX); + static int mpc52xx_uart_startup(struct uart_port *port) { @@ -510,7 +531,7 @@ mpc52xx_uart_startup(struct uart_port *port) return ret; /* Reset/activate the port, clear and enable interrupts */ - out_8(&psc->command, MPC52xx_PSC_RST_RX); + mpc52xx_uart_reset_rx(DONT_LOCK); out_8(&psc->command, MPC52xx_PSC_RST_TX); out_be32(&psc->sicr, 0); /* UART mode DCD ignored */ @@ -529,7 +550,7 @@ mpc52xx_uart_shutdown(struct uart_port *port) struct mpc52xx_psc __iomem *psc = PSC(port); /* Shut down the port. Leave TX active if on a console port */ - out_8(&psc->command, MPC52xx_PSC_RST_RX); + mpc52xx_uart_reset_rx(DONT_LOCK); if (!uart_console(port)) out_8(&psc->command, MPC52xx_PSC_RST_TX); @@ -588,9 +609,6 @@ mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new, /* Get the lock */ spin_lock_irqsave(&port->lock, flags); - /* Update the per-port timeout */ - uart_update_timeout(port, new->c_cflag, baud); - /* Do our best to flush TX & RX, so we don't loose anything */ /* But we don't wait indefinitly ! */ j = 5000000; /* Maximum wait */ @@ -607,9 +625,12 @@ mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new, "Some chars may have been lost.\n"); /* Reset the TX & RX */ - out_8(&psc->command, MPC52xx_PSC_RST_RX); + mpc52xx_uart_reset_rx(LOCK); out_8(&psc->command, MPC52xx_PSC_RST_TX); + /* Update the per-port timeout */ + uart_update_timeout(port, new->c_cflag, baud); + /* Send new mode settings */ out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1); out_8(&psc->mode, mr1);