From patchwork Tue Sep 11 17:06:31 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caraman Mihai Claudiu-B02008 X-Patchwork-Id: 183157 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 0B7892C03CA for ; Wed, 12 Sep 2012 03:07:14 +1000 (EST) Received: from tx2outboundpool.messaging.microsoft.com (tx2ehsobe003.messaging.microsoft.com [65.55.88.13]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id BF2BC2C0085 for ; Wed, 12 Sep 2012 03:06:44 +1000 (EST) Received: from mail133-tx2-R.bigfish.com (10.9.14.248) by TX2EHSOBE010.bigfish.com (10.9.40.30) with Microsoft SMTP Server id 14.1.225.23; Tue, 11 Sep 2012 17:06:40 +0000 Received: from mail133-tx2 (localhost [127.0.0.1]) by mail133-tx2-R.bigfish.com (Postfix) with ESMTP id 86EEF340175; Tue, 11 Sep 2012 17:06:40 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: -6 X-BigFish: VS-6(zz1432I41c5Nzz1202h1d1ahzzz2dh2a8h668h839h8e2h8e3h944hd25hf0ah107ah1220h1288h12a5h12a9h12bdhbe9i1155h) Received: from mail133-tx2 (localhost.localdomain [127.0.0.1]) by mail133-tx2 (MessageSwitch) id 1347383198693676_30656; Tue, 11 Sep 2012 17:06:38 +0000 (UTC) Received: from TX2EHSMHS024.bigfish.com (unknown [10.9.14.242]) by mail133-tx2.bigfish.com (Postfix) with ESMTP id 939234E0042; Tue, 11 Sep 2012 17:06:38 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS024.bigfish.com (10.9.99.124) with Microsoft SMTP Server (TLS) id 14.1.225.23; Tue, 11 Sep 2012 17:06:32 +0000 Received: from 039-SN2MPN1-011.039d.mgd.msft.net ([169.254.1.212]) by 039-SN1MMR1-001.039d.mgd.msft.net ([10.84.1.13]) with mapi id 14.02.0309.003; Tue, 11 Sep 2012 12:06:32 -0500 From: Caraman Mihai Claudiu-B02008 To: Wood Scott-B07421 , "benh@kernel.crashing.org" , "galak@kernel.crashing.org" Subject: RE: [PATCH 2/2] powerpc/e6500: TLB miss handler with hardware tablewalk support Thread-Topic: [PATCH 2/2] powerpc/e6500: TLB miss handler with hardware tablewalk support Thread-Index: AQHNSoeHrzLPnaKUOkiS12XmhvK8c5eF5cmA Date: Tue, 11 Sep 2012 17:06:31 +0000 Message-ID: <300B73AA675FCE4A93EB4FC1D42459FF1DC945@039-SN2MPN1-011.039d.mgd.msft.net> References: <20120614234101.GB17147@tyr.buserror.net> In-Reply-To: <20120614234101.GB17147@tyr.buserror.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.171.73.132] MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: "linuxppc-dev@lists.ozlabs.org" X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" > diff --git a/arch/powerpc/mm/tlb_low_64e.S > b/arch/powerpc/mm/tlb_low_64e.S > index efe0f33..8e82772 100644 > --- a/arch/powerpc/mm/tlb_low_64e.S > +++ b/arch/powerpc/mm/tlb_low_64e.S > @@ -232,6 +232,173 @@ itlb_miss_fault_bolted: > beq tlb_miss_common_bolted > b itlb_miss_kernel_bolted > > +/* > + * TLB miss handling for e6500 and derivatives, using hardware > tablewalk. > + * > + * Linear mapping is bolted: no virtual page table or nested TLB misses > + * Indirect entries in TLB1, hardware loads resulting direct entries > + * into TLB0 > + * No HES or NV hint on TLB1, so we need to do software round-robin > + * No tlbsrx. so we need a spinlock, and we have to deal > + * with MAS-damage caused by tlbsx > + * 4K pages only > + */ > + > + START_EXCEPTION(instruction_tlb_miss_e6500) > + tlb_prolog_bolted SPRN_SRR0 > + > + ld r11,PACA_TLB_PER_CORE_PTR(r13) > + srdi. r15,r16,60 /* get region */ > + ori r16,r16,1 > + > + TLB_MISS_STATS_SAVE_INFO_BOLTED > + bne tlb_miss_kernel_e6500 /* user/kernel test */ > + > + b tlb_miss_common_e6500 > + > + START_EXCEPTION(data_tlb_miss_e6500) > + tlb_prolog_bolted SPRN_DEAR > + > + ld r11,PACA_TLB_PER_CORE_PTR(r13) > + srdi. r15,r16,60 /* get region */ > + rldicr r16,r16,0,62 > + > + TLB_MISS_STATS_SAVE_INFO_BOLTED > + bne tlb_miss_kernel_e6500 /* user vs kernel check */ > + This ends up calling DO_KVM macro twice with same parameters which generates the following compile error: arch/powerpc/mm/tlb_low_64e.S:307: Error: symbol `kvmppc_resume_14_0x01B' is already defined arch/powerpc/mm/tlb_low_64e.S:319: Error: symbol `kvmppc_resume_13_0x01B' is already defined We can live with it if we patch DO_KVM like this: -Mike diff --git a/arch/powerpc/include/asm/kvm_booke_hv_asm.h b/arch/powerpc/include/asm/kvm_booke_hv_asm.h index 4610fb0..029ecab 100644 --- a/arch/powerpc/include/asm/kvm_booke_hv_asm.h +++ b/arch/powerpc/include/asm/kvm_booke_hv_asm.h @@ -55,9 +55,9 @@ #ifdef CONFIG_KVM_BOOKE_HV BEGIN_FTR_SECTION mtocrf 0x80, r11 /* check MSR[GS] without clobbering reg */ - bf 3, kvmppc_resume_\intno\()_\srr1 + bf 3, 1f b kvmppc_handler_\intno\()_\srr1 -kvmppc_resume_\intno\()_\srr1: +1: END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) #endif .endm