From patchwork Thu Jul 9 23:24:38 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Doug Thompson X-Patchwork-Id: 29645 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@bilbo.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from ozlabs.org (ozlabs.org [203.10.76.45]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mx.ozlabs.org", Issuer "CA Cert Signing Authority" (verified OK)) by bilbo.ozlabs.org (Postfix) with ESMTPS id E8E46B707D for ; Fri, 10 Jul 2009 09:31:57 +1000 (EST) Received: by ozlabs.org (Postfix) id DBA48DDDF7; Fri, 10 Jul 2009 09:31:57 +1000 (EST) Delivered-To: patchwork-incoming@ozlabs.org Received: from bilbo.ozlabs.org (bilbo.ozlabs.org [203.10.76.25]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "bilbo.ozlabs.org", Issuer "CAcert Class 3 Root" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id CDAD6DDDE1 for ; Fri, 10 Jul 2009 09:31:57 +1000 (EST) Received: from bilbo.ozlabs.org (localhost [127.0.0.1]) by bilbo.ozlabs.org (Postfix) with ESMTP id C87DBB72BB for ; Fri, 10 Jul 2009 09:31:32 +1000 (EST) Received: from ozlabs.org (ozlabs.org [203.10.76.45]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mx.ozlabs.org", Issuer "CA Cert Signing Authority" (verified OK)) by bilbo.ozlabs.org (Postfix) with ESMTPS id 8E230B7079 for ; Fri, 10 Jul 2009 09:31:21 +1000 (EST) Received: by ozlabs.org (Postfix) id 7CE27DDDF8; Fri, 10 Jul 2009 09:31:21 +1000 (EST) Delivered-To: linuxppc-dev@ozlabs.org X-Greylist: delayed 398 seconds by postgrey-1.31 at ozlabs; Fri, 10 Jul 2009 09:31:20 EST Received: from web50111.mail.re2.yahoo.com (web50111.mail.re2.yahoo.com [206.190.39.137]) by ozlabs.org (Postfix) with SMTP id 7313EDDDF6 for ; Fri, 10 Jul 2009 09:31:20 +1000 (EST) Received: (qmail 45732 invoked by uid 60001); 9 Jul 2009 23:24:39 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yahoo.com; s=s1024; t=1247181879; bh=HvvaZNHj23nsG37w6I3XAsp4WlgRrULeugM6PCwomg0=; h=Message-ID:X-YMail-OSG:Received:X-Mailer:Date:From:Subject:To:MIME-Version:Content-Type:Content-Transfer-Encoding; b=FqQqXJnahA/W2yLIaNfp02g0mEFaO3jDiuo/nJDfO1ECqT6mxgse6EaEoBuSgwglk02z8M67U8K5GqEUj/BZSPf6HA/Wlqqwb9r6+Ted/5cIAbrk2Gy0cacHEsxTa8ynupC02V4NH97eomqOwFHi9FovPPnHvplw6/rIsExv1A4= DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.com; h=Message-ID:X-YMail-OSG:Received:X-Mailer:Date:From:Subject:To:MIME-Version:Content-Type:Content-Transfer-Encoding; b=YWFSrUtBf0BjAPt0evx/bE4fZ/AgvUWIqmP8y1gMFgkDLqL8wH24+GsLT1AWqqG6hN9IZ5uUYuM7ZduGzofTAgFl2PyVUV9u58mxReCcuk5J2PatCwG9MiVxnq3lbiLxeXFca4az23d39O+25+VD7DenXoxbkclZFMQlNeScu3g=; Message-ID: <2576.44687.qm@web50111.mail.re2.yahoo.com> X-YMail-OSG: D7XJFR4VM1lP40W9rprcEkkqksnMdcFA5ng91d5rDveiA69maV0- Received: from [198.65.168.24] by web50111.mail.re2.yahoo.com via HTTP; Thu, 09 Jul 2009 16:24:38 PDT X-Mailer: YahooMailClassic/6.0.18 YahooMailWebService/0.7.289.15 Date: Thu, 9 Jul 2009 16:24:38 -0700 (PDT) From: Doug Thompson Subject: Re: [PATCH v2] edac: mpc85xx: add support for mpc83xx memory controller To: bluesmoke-devel@lists.sourceforge.net, Dave Jiang , Kumar Gala , linuxppc-dev@ozlabs.org, "Ira W. Snyder" MIME-Version: 1.0 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Ok, is this the one you want me to push upstream? doug t --- On Thu, 7/9/09, Ira W. Snyder wrote: From: Ira W. Snyder Subject: [PATCH v2] edac: mpc85xx: add support for mpc83xx memory controller To: bluesmoke-devel@lists.sourceforge.net, "Dave Jiang" , "Kumar Gala" , linuxppc-dev@ozlabs.org Date: Thursday, July 9, 2009, 1:40 PM Add support for the Freescale MPC83xx memory controller to the existing driver for the Freescale MPC85xx memory controller. The only difference between the two processors are in the CS_BNDS register parsing code, which has been changed so it will work on both processors. The L2 cache controller does not exist on the MPC83xx, but the OF subsystem will not use the driver if the device is not present in the OF device tree. Signed-off-by: Ira W. Snyder --- Kumar, I had to change the nr_pages calculation to make the math work out. I checked it on my board and did the math by hand for a 64GB 85xx using 64K pages. In both cases, nr_pages * PAGE_SIZE comes out to the correct value. Thanks for the help. v1 -> v2:   * Use PAGE_SHIFT to parse cs_bnds regardless of board type   * Remove special-casing for the 83xx processor drivers/edac/Kconfig        |    6 +++--- drivers/edac/mpc85xx_edac.c |   28 +++++++++++++++++++--------- 2 files changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 4339b1a..78303f9 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -176,11 +176,11 @@ config EDAC_I5100       San Clemente MCH. config EDAC_MPC85XX -    tristate "Freescale MPC85xx" -    depends on EDAC_MM_EDAC && FSL_SOC && MPC85xx +    tristate "Freescale MPC83xx / MPC85xx" +    depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || MPC85xx)     help       Support for error detection and correction on the Freescale -      MPC8560, MPC8540, MPC8548 +      MPC8349, MPC8560, MPC8540, MPC8548 config EDAC_MV64X60     tristate "Marvell MV64x60" diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c index b4f5c63..ba2a264 100644 --- a/drivers/edac/mpc85xx_edac.c +++ b/drivers/edac/mpc85xx_edac.c @@ -43,7 +43,9 @@ static u32 orig_pci_err_en; #endif static u32 orig_l2_err_disable; +#ifdef CONFIG_MPC85xx static u32 orig_hid1[2]; +#endif /************************ MC SYSFS parts ***********************************/ @@ -790,19 +792,20 @@ static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci)         csrow = &mci->csrows[index];         cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 +                   (index * MPC85XX_MC_CS_BNDS_OFS)); -        start = (cs_bnds & 0xfff0000) << 4; -        end = ((cs_bnds & 0xfff) << 20); -        if (start) -            start |= 0xfffff; -        if (end) -            end |= 0xfffff; + +        start = (cs_bnds & 0xffff0000) >> 16; +        end   = (cs_bnds & 0x0000ffff);         if (start == end)             continue;    /* not populated */ +        start <<= (24 - PAGE_SHIFT); +        end   <<= (24 - PAGE_SHIFT); +        end    |= (1 << (24 - PAGE_SHIFT)) - 1; +         csrow->first_page = start >> PAGE_SHIFT;         csrow->last_page = end >> PAGE_SHIFT; -        csrow->nr_pages = csrow->last_page + 1 - csrow->first_page; +        csrow->nr_pages = end + 1 - start;         csrow->grain = 8;         csrow->mtype = mtype;         csrow->dtype = DEV_UNKNOWN; @@ -986,6 +989,7 @@ static struct of_device_id mpc85xx_mc_err_of_match[] = {     { .compatible = "fsl,mpc8560-memory-controller", },     { .compatible = "fsl,mpc8568-memory-controller", },     { .compatible = "fsl,mpc8572-memory-controller", }, +    { .compatible = "fsl,mpc8349-memory-controller", },     {}, }; @@ -1001,13 +1005,13 @@ static struct of_platform_driver mpc85xx_mc_err_driver = {            }, }; - +#ifdef CONFIG_MPC85xx static void __init mpc85xx_mc_clear_rfxe(void *data) {     orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1);     mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~0x20000)); } - +#endif static int __init mpc85xx_mc_init(void) { @@ -1040,26 +1044,32 @@ static int __init mpc85xx_mc_init(void)         printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n"); #endif +#ifdef CONFIG_MPC85xx     /*      * need to clear HID1[RFXE] to disable machine check int      * so we can catch it      */     if (edac_op_state == EDAC_OPSTATE_INT)         on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0); +#endif     return 0; } module_init(mpc85xx_mc_init); +#ifdef CONFIG_MPC85xx static void __exit mpc85xx_mc_restore_hid1(void *data) {     mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]); } +#endif static void __exit mpc85xx_mc_exit(void) { +#ifdef CONFIG_MPC85xx     on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0); +#endif #ifdef CONFIG_PCI     of_unregister_platform_driver(&mpc85xx_pci_err_driver); #endif