| Message ID | 20240808071132.149251-9-herve.codina@bootlin.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Christophe Leroy |
| Headers | show |
| Series | soc: fsl: Add support for QUICC Engine TSA and QMC | expand |
Le 08/08/2024 à 09:11, Herve Codina a écrit : > SISTR, SICMR and SIRP registers offset definitions are not used. > > In order to avoid unneeded code, remove them. > > Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> > --- > drivers/soc/fsl/qe/tsa.c | 9 --------- > 1 file changed, 9 deletions(-) > > diff --git a/drivers/soc/fsl/qe/tsa.c b/drivers/soc/fsl/qe/tsa.c > index a9d35b44489d..244d521d8780 100644 > --- a/drivers/soc/fsl/qe/tsa.c > +++ b/drivers/soc/fsl/qe/tsa.c > @@ -66,12 +66,6 @@ > #define TSA_SIGMR_RDM_STATIC_TDMAB FIELD_PREP_CONST(TSA_SIGMR_RDM_MASK, 0x2) > #define TSA_SIGMR_RDM_DYN_TDMAB FIELD_PREP_CONST(TSA_SIGMR_RDM_MASK, 0x3) > > -/* SI status register (8 bits) */ > -#define TSA_SISTR 0x06 > - > -/* SI command register (8 bits) */ > -#define TSA_SICMR 0x07 > - > /* SI clock route register (32 bits) */ > #define TSA_SICR 0x0C > #define TSA_SICR_SCC2_MASK GENMASK(15, 8) > @@ -102,9 +96,6 @@ > #define TSA_SICR_SCC_TXCS_CLK37 FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x6) > #define TSA_SICR_SCC_TXCS_CLK48 FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x7) > > -/* Serial interface RAM pointer register (32 bits) */ > -#define TSA_SIRP 0x10 > - > struct tsa_entries_area { > void __iomem *entries_start; > void __iomem *entries_next;
diff --git a/drivers/soc/fsl/qe/tsa.c b/drivers/soc/fsl/qe/tsa.c index a9d35b44489d..244d521d8780 100644 --- a/drivers/soc/fsl/qe/tsa.c +++ b/drivers/soc/fsl/qe/tsa.c @@ -66,12 +66,6 @@ #define TSA_SIGMR_RDM_STATIC_TDMAB FIELD_PREP_CONST(TSA_SIGMR_RDM_MASK, 0x2) #define TSA_SIGMR_RDM_DYN_TDMAB FIELD_PREP_CONST(TSA_SIGMR_RDM_MASK, 0x3) -/* SI status register (8 bits) */ -#define TSA_SISTR 0x06 - -/* SI command register (8 bits) */ -#define TSA_SICMR 0x07 - /* SI clock route register (32 bits) */ #define TSA_SICR 0x0C #define TSA_SICR_SCC2_MASK GENMASK(15, 8) @@ -102,9 +96,6 @@ #define TSA_SICR_SCC_TXCS_CLK37 FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x6) #define TSA_SICR_SCC_TXCS_CLK48 FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x7) -/* Serial interface RAM pointer register (32 bits) */ -#define TSA_SIRP 0x10 - struct tsa_entries_area { void __iomem *entries_start; void __iomem *entries_next;
SISTR, SICMR and SIRP registers offset definitions are not used. In order to avoid unneeded code, remove them. Signed-off-by: Herve Codina <herve.codina@bootlin.com> --- drivers/soc/fsl/qe/tsa.c | 9 --------- 1 file changed, 9 deletions(-)