| Message ID | 20240729142107.104574-8-herve.codina@bootlin.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere, archived |
| Delegated to: | Christophe Leroy |
| Headers | show |
| Series | soc: fsl: Add support for QUICC Engine TSA and QMC | expand |
On Mon, Jul 29, 2024 at 04:20:36PM +0200, Herve Codina wrote: > Add support for the time slot assigner (TSA) available in some > PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321. > > This QE TSA is similar to the CPM TSA except that it uses UCCs (Unified > Communication Controllers) instead of SCCs (Serial Communication > Controllers). Also, compared against the CPM TSA, this QE TSA can handle > up to 4 TDMs instead of 2 and allows to configure the logic level of > sync signals. > > Signed-off-by: Herve Codina <herve.codina@bootlin.com> > --- > .../bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml | 212 ++++++++++++++++++ > include/dt-bindings/soc/qe-fsl,tsa.h | 13 ++ > 2 files changed, 225 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml > create mode 100644 include/dt-bindings/soc/qe-fsl,tsa.h > > diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml > new file mode 100644 > index 000000000000..569a4d2e0cab > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml > @@ -0,0 +1,212 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: PowerQUICC QE Time-slot assigner (TSA) controller > + > +maintainers: > + - Herve Codina <herve.codina@bootlin.com> > + > +description: > + The TSA is the time-slot assigner that can be found on some PowerQUICC SoC. > + Its purpose is to route some TDM time-slots to other internal serial > + controllers. > + > +properties: > + compatible: > + items: > + - enum: > + - fsl,mpc8321-tsa > + - const: fsl,qe-tsa > + > + reg: > + items: > + - description: SI (Serial Interface) register base > + - description: SI RAM base > + > + reg-names: > + items: > + - const: si_regs > + - const: si_ram > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > +patternProperties: > + '^tdm@[0-3]$': > + description: > + The TDM managed by this controller > + type: object > + > + additionalProperties: false > + > + properties: > + reg: > + minimum: 0 > + maximum: 3 > + description: > + The TDM number for this TDM, 0 for TDMa, 1 for TDMb, 2 for TDMc and 3 > + for TDMd. > + > + fsl,common-rxtx-pins: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + The hardware can use four dedicated pins for Tx clock, Tx sync, Rx > + clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync. > + Without the 'fsl,common-rxtx-pins' property, the four pins are used. > + With the 'fsl,common-rxtx-pins' property, two pins are used. > + > + clocks: > + minItems: 2 > + items: > + - description: Receive sync clock > + - description: Receive data clock > + - description: Transmit sync clock > + - description: Transmit data clock > + > + clock-names: > + minItems: 2 > + items: > + - const: rsync > + - const: rclk > + - const: tsync > + - const: tclk > + > + fsl,rx-frame-sync-delay-bits: > + enum: [0, 1, 2, 3] > + default: 0 > + description: | > + Receive frame sync delay in number of bits. > + Indicates the delay between the Rx sync and the first bit of the Rx > + frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay. The last 2 sentences seem redundant to me. > + > + fsl,tx-frame-sync-delay-bits: > + enum: [0, 1, 2, 3] > + default: 0 > + description: | > + Transmit frame sync delay in number of bits. > + Indicates the delay between the Tx sync and the first bit of the Tx > + frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay. > + > + fsl,clock-falling-edge: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + Data is sent on falling edge of the clock (and received on the rising > + edge). If 'clock-falling-edge' is not present, data is sent on the No such property 'clock-falling-edge'. I don't think you need to repeat the property name anyways. > + rising edge (and received on the falling edge). > + > + fsl,fsync-rising-edge: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + Frame sync pulses are sampled with the rising edge of the channel > + clock. If 'fsync-rising-edge' is not present, pulses are sampled with And same here. > + the falling edge. > + > + fsl,fsync-active-low: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + Frame sync signals are active on low logic level. > + If 'fsync-active-low' is not present, sync signals are active on high And here... > + level. > + > + fsl,double-speed-clock: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + The channel clock is twice the data rate. > + > + patternProperties: > + '^fsl,[rt]x-ts-routes$': > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > + description: | > + A list of tuple that indicates the Tx or Rx time-slots routes. > + items: > + items: > + - description: > + The number of time-slots > + minimum: 1 > + maximum: 64 > + - description: | > + The source (Tx) or destination (Rx) serial interface > + (dt-bindings/soc/qe-fsl,tsa.h defines these values) > + - 0: No destination > + - 1: UCC1 > + - 2: UCC2 > + - 3: UCC3 > + - 4: UCC4 > + - 5: UCC5 > + enum: [0, 1, 2, 3, 4, 5] > + minItems: 1 > + maxItems: 64 > + > + allOf: > + # If fsl,common-rxtx-pins is present, only 2 clocks are needed. > + # Else, the 4 clocks must be present. > + - if: > + required: > + - fsl,common-rxtx-pins > + then: > + properties: > + clocks: > + maxItems: 2 > + clock-names: > + maxItems: 2 > + else: > + properties: > + clocks: > + minItems: 4 > + clock-names: > + minItems: 4 > + > + required: > + - reg > + - clocks > + - clock-names > + > +required: > + - compatible > + - reg > + - reg-names > + - '#address-cells' > + - '#size-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/soc/qe-fsl,tsa.h> > + > + tsa@ae0 { > + compatible = "fsl,mpc8321-tsa", "fsl,qe-tsa"; > + reg = <0xae0 0x10>, > + <0xc00 0x200>; > + reg-names = "si_regs", "si_ram"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + tdm@0 { > + /* TDMa */ > + reg = <0>; > + > + clocks = <&clk_l1rsynca>, <&clk_l1rclka>; > + clock-names = "rsync", "rclk"; > + > + fsl,common-rxtx-pins; > + fsl,fsync-rising-edge; > + > + fsl,tx-ts-routes = <2 0>, /* TS 0..1 */ > + <24 FSL_QE_TSA_UCC4>, /* TS 2..25 */ > + <1 0>, /* TS 26 */ > + <5 FSL_QE_TSA_UCC3>; /* TS 27..31 */ > + > + fsl,rx-ts-routes = <2 0>, /* TS 0..1 */ > + <24 FSL_QE_TSA_UCC4>, /* 2..25 */ > + <1 0>, /* TS 26 */ > + <5 FSL_QE_TSA_UCC3>; /* TS 27..31 */ > + }; > + }; > diff --git a/include/dt-bindings/soc/qe-fsl,tsa.h b/include/dt-bindings/soc/qe-fsl,tsa.h > new file mode 100644 > index 000000000000..3cf3df9c0968 > --- /dev/null > +++ b/include/dt-bindings/soc/qe-fsl,tsa.h > @@ -0,0 +1,13 @@ > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ > + > +#ifndef __DT_BINDINGS_SOC_FSL_QE_TSA_H > +#define __DT_BINDINGS_SOC_FSL_QE_TSA_H > + > +#define FSL_QE_TSA_NU 0 > +#define FSL_QE_TSA_UCC1 1 > +#define FSL_QE_TSA_UCC2 2 > +#define FSL_QE_TSA_UCC3 3 > +#define FSL_QE_TSA_UCC4 4 > +#define FSL_QE_TSA_UCC5 5 > + > +#endif > -- > 2.45.0 >
diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml new file mode 100644 index 000000000000..569a4d2e0cab --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml @@ -0,0 +1,212 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PowerQUICC QE Time-slot assigner (TSA) controller + +maintainers: + - Herve Codina <herve.codina@bootlin.com> + +description: + The TSA is the time-slot assigner that can be found on some PowerQUICC SoC. + Its purpose is to route some TDM time-slots to other internal serial + controllers. + +properties: + compatible: + items: + - enum: + - fsl,mpc8321-tsa + - const: fsl,qe-tsa + + reg: + items: + - description: SI (Serial Interface) register base + - description: SI RAM base + + reg-names: + items: + - const: si_regs + - const: si_ram + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + '^tdm@[0-3]$': + description: + The TDM managed by this controller + type: object + + additionalProperties: false + + properties: + reg: + minimum: 0 + maximum: 3 + description: + The TDM number for this TDM, 0 for TDMa, 1 for TDMb, 2 for TDMc and 3 + for TDMd. + + fsl,common-rxtx-pins: + $ref: /schemas/types.yaml#/definitions/flag + description: + The hardware can use four dedicated pins for Tx clock, Tx sync, Rx + clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync. + Without the 'fsl,common-rxtx-pins' property, the four pins are used. + With the 'fsl,common-rxtx-pins' property, two pins are used. + + clocks: + minItems: 2 + items: + - description: Receive sync clock + - description: Receive data clock + - description: Transmit sync clock + - description: Transmit data clock + + clock-names: + minItems: 2 + items: + - const: rsync + - const: rclk + - const: tsync + - const: tclk + + fsl,rx-frame-sync-delay-bits: + enum: [0, 1, 2, 3] + default: 0 + description: | + Receive frame sync delay in number of bits. + Indicates the delay between the Rx sync and the first bit of the Rx + frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay. + + fsl,tx-frame-sync-delay-bits: + enum: [0, 1, 2, 3] + default: 0 + description: | + Transmit frame sync delay in number of bits. + Indicates the delay between the Tx sync and the first bit of the Tx + frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay. + + fsl,clock-falling-edge: + $ref: /schemas/types.yaml#/definitions/flag + description: + Data is sent on falling edge of the clock (and received on the rising + edge). If 'clock-falling-edge' is not present, data is sent on the + rising edge (and received on the falling edge). + + fsl,fsync-rising-edge: + $ref: /schemas/types.yaml#/definitions/flag + description: + Frame sync pulses are sampled with the rising edge of the channel + clock. If 'fsync-rising-edge' is not present, pulses are sampled with + the falling edge. + + fsl,fsync-active-low: + $ref: /schemas/types.yaml#/definitions/flag + description: + Frame sync signals are active on low logic level. + If 'fsync-active-low' is not present, sync signals are active on high + level. + + fsl,double-speed-clock: + $ref: /schemas/types.yaml#/definitions/flag + description: + The channel clock is twice the data rate. + + patternProperties: + '^fsl,[rt]x-ts-routes$': + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: | + A list of tuple that indicates the Tx or Rx time-slots routes. + items: + items: + - description: + The number of time-slots + minimum: 1 + maximum: 64 + - description: | + The source (Tx) or destination (Rx) serial interface + (dt-bindings/soc/qe-fsl,tsa.h defines these values) + - 0: No destination + - 1: UCC1 + - 2: UCC2 + - 3: UCC3 + - 4: UCC4 + - 5: UCC5 + enum: [0, 1, 2, 3, 4, 5] + minItems: 1 + maxItems: 64 + + allOf: + # If fsl,common-rxtx-pins is present, only 2 clocks are needed. + # Else, the 4 clocks must be present. + - if: + required: + - fsl,common-rxtx-pins + then: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + else: + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + + required: + - reg + - clocks + - clock-names + +required: + - compatible + - reg + - reg-names + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/soc/qe-fsl,tsa.h> + + tsa@ae0 { + compatible = "fsl,mpc8321-tsa", "fsl,qe-tsa"; + reg = <0xae0 0x10>, + <0xc00 0x200>; + reg-names = "si_regs", "si_ram"; + + #address-cells = <1>; + #size-cells = <0>; + + tdm@0 { + /* TDMa */ + reg = <0>; + + clocks = <&clk_l1rsynca>, <&clk_l1rclka>; + clock-names = "rsync", "rclk"; + + fsl,common-rxtx-pins; + fsl,fsync-rising-edge; + + fsl,tx-ts-routes = <2 0>, /* TS 0..1 */ + <24 FSL_QE_TSA_UCC4>, /* TS 2..25 */ + <1 0>, /* TS 26 */ + <5 FSL_QE_TSA_UCC3>; /* TS 27..31 */ + + fsl,rx-ts-routes = <2 0>, /* TS 0..1 */ + <24 FSL_QE_TSA_UCC4>, /* 2..25 */ + <1 0>, /* TS 26 */ + <5 FSL_QE_TSA_UCC3>; /* TS 27..31 */ + }; + }; diff --git a/include/dt-bindings/soc/qe-fsl,tsa.h b/include/dt-bindings/soc/qe-fsl,tsa.h new file mode 100644 index 000000000000..3cf3df9c0968 --- /dev/null +++ b/include/dt-bindings/soc/qe-fsl,tsa.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ + +#ifndef __DT_BINDINGS_SOC_FSL_QE_TSA_H +#define __DT_BINDINGS_SOC_FSL_QE_TSA_H + +#define FSL_QE_TSA_NU 0 +#define FSL_QE_TSA_UCC1 1 +#define FSL_QE_TSA_UCC2 2 +#define FSL_QE_TSA_UCC3 3 +#define FSL_QE_TSA_UCC4 4 +#define FSL_QE_TSA_UCC5 5 + +#endif
Add support for the time slot assigner (TSA) available in some PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321. This QE TSA is similar to the CPM TSA except that it uses UCCs (Unified Communication Controllers) instead of SCCs (Serial Communication Controllers). Also, compared against the CPM TSA, this QE TSA can handle up to 4 TDMs instead of 2 and allows to configure the logic level of sync signals. Signed-off-by: Herve Codina <herve.codina@bootlin.com> --- .../bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml | 212 ++++++++++++++++++ include/dt-bindings/soc/qe-fsl,tsa.h | 13 ++ 2 files changed, 225 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml create mode 100644 include/dt-bindings/soc/qe-fsl,tsa.h