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Mon, 4 Dec 2023 16:08:56 +0000 From: Frank Li To: manivannan.sadhasivam@linaro.org Subject: [PATCH v6 2/4] PCI: layerscape: Add suspend/resume for ls1021a Date: Mon, 4 Dec 2023 11:08:27 -0500 Message-Id: <20231204160829.2498703-3-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231204160829.2498703-1-Frank.Li@nxp.com> References: <20231204160829.2498703-1-Frank.Li@nxp.com> X-ClientProxiedBy: BYAPR21CA0027.namprd21.prod.outlook.com (2603:10b6:a03:114::37) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DBBPR04MB8057:EE_ X-MS-Office365-Filtering-Correlation-Id: c32978ae-40cb-4e11-9511-08dbf4e35135 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: i58ffvXUsX7sFZvGdZTQl/c0xBpEVLodzgmaRGO8FVoKddfBCB99IS4qJLhmC/kwCdWIzkefW1EVG4Eqmv2lpf7VcicXQyGtvcY20EGIELamF5MY9ttCCc1hgcNzjnJtDxWG+KSDgukVY9b9/EMSpXeFp5Jr5a6+bOZQBAjQzK+fQzU+HccAgZ7GlbZX3UY4qkzTzs0pomdTT5etmUj61503Dc2o9tjCMhxojlBGOjIJJhmkzPBiZCsak+guBKhJK7fKHK6otPhGhOQWZfR32fOKk7b99CpNPFXvLIihzVa5ZzXK6jorUKzHSvKAuEs+O5HSCS53vp+zpeP4t2cBCYSLwPLwJunslpn8Vlsswxmh4Aw8ftlRNtIsUFwbpuUf1vUVyBYXF7j13P0BtF8K3OOeNY1cY5FQnn4FlWPUNeshZWiMdezbGMkcmK3kSzeUTDq/WaC9h2yHC3xpr63MdCLIpsPG6xpiNlR9n2+DV/KZ7Va+7m6qc3dlbjjAJmuUVTWJF/dk0bD5lE8hst1UF1hHpT0rLIb1/NLf92niiNc1qDT5tcYMct8wEiaG6lh5Dvu9bljTbE9E0WK8c8wDbAW5fA3w+pYNFJeRmhFTI6H692QkT2RtytIq/wAui4Ei X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:AM6PR04MB4838.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(396003)(136003)(39860400002)(366004)(376002)(346002)(230922051799003)(64100799003)(451199024)(1800799012)(186009)(6916009)(66556008)(66476007)(8936002)(316002)(86362001)(8676002)(4326008)(6486002)(478600001)(66946007)(36756003)(41300700001)(38350700005)(15650500001)(2906002)(7416002)(5660300002)(26005)(2616005)(1076003)(6506007)(6512007)(52116002)(83380400001)(6666004)(38100700002);DIR:OUT;SFP:1101; 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In the suspend path, PME_Turn_Off message is sent to the endpoint to transition the link to L2/L3_Ready state. In this SoC, there is no way to check if the controller has received the PME_To_Ack from the endpoint or not. So to be on the safer side, the driver just waits for PCIE_PME_TO_L2_TIMEOUT_US before asserting the SoC specific PMXMTTURNOFF bit to complete the PME_Turn_Off handshake. Then the link would enter L2/L3 state depending on the VAUX supply. In the resume path, the link is brought back from L2 to L0 by doing a software reset. Acked-by: Roy Zang Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- Notes: Change from v5 to v6 - remove reduntant pci->pp.ops = &ls_pcie_host_ops; Change from v4 to v5 - update comit message - remove a empty line - use comments /* Reset the PEX wrapper to bring the link out of L2 */ - pci->pp.ops = pcie->drvdata->ops, ls_pcie_host_ops to the "ops" member of layerscape_drvdata. - don't set pcie->scfg = NULL at error path Change from v3 to v4 - update commit message. - it is reset a glue logic part for PCI controller. - use regmap_write_bits() to reduce code change. Change from v2 to v3 - update according to mani's feedback change from v1 to v2 - change subject 'a' to 'A' drivers/pci/controller/dwc/pci-layerscape.c | 83 ++++++++++++++++++++- 1 file changed, 80 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index aea89926bcc4f..711563777aeba 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -35,11 +35,19 @@ #define PF_MCR_PTOMR BIT(0) #define PF_MCR_EXL2S BIT(1) +/* LS1021A PEXn PM Write Control Register */ +#define SCFG_PEXPMWRCR(idx) (0x5c + (idx) * 0x64) +#define PMXMTTURNOFF BIT(31) +#define SCFG_PEXSFTRSTCR 0x190 +#define PEXSR(idx) BIT(idx) + #define PCIE_IATU_NUM 6 struct ls_pcie_drvdata { const u32 pf_off; + const struct dw_pcie_host_ops *ops; int (*exit_from_l2)(struct dw_pcie_rp *pp); + bool scfg_support; bool pm_support; }; @@ -47,6 +55,8 @@ struct ls_pcie { struct dw_pcie *pci; const struct ls_pcie_drvdata *drvdata; void __iomem *pf_base; + struct regmap *scfg; + int index; bool big_endian; }; @@ -171,18 +181,70 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp) return 0; } +static void scfg_pcie_send_turnoff_msg(struct regmap *scfg, u32 reg, u32 mask) +{ + /* Send PME_Turn_Off message */ + regmap_write_bits(scfg, reg, mask, mask); + + /* + * There is no specific register to check for PME_To_Ack from endpoint. + * So on the safe side, wait for PCIE_PME_TO_L2_TIMEOUT_US. + */ + mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000); + + /* + * Layerscape hardware reference manual recommends clearing the PMXMTTURNOFF bit + * to complete the PME_Turn_Off handshake. + */ + regmap_write_bits(scfg, reg, mask, 0); +} + +static void ls1021a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + + scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), PMXMTTURNOFF); +} + +static int scfg_pcie_exit_from_l2(struct regmap *scfg, u32 reg, u32 mask) +{ + /* Reset the PEX wrapper to bring the link out of L2 */ + regmap_write_bits(scfg, reg, mask, mask); + regmap_write_bits(scfg, reg, mask, 0); + + return 0; +} + +static int ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + + return scfg_pcie_exit_from_l2(pcie->scfg, SCFG_PEXSFTRSTCR, PEXSR(pcie->index)); +} + static const struct dw_pcie_host_ops ls_pcie_host_ops = { .host_init = ls_pcie_host_init, .pme_turn_off = ls_pcie_send_turnoff_msg, }; +static const struct dw_pcie_host_ops ls1021a_pcie_host_ops = { + .host_init = ls_pcie_host_init, + .pme_turn_off = ls1021a_pcie_send_turnoff_msg, +}; + static const struct ls_pcie_drvdata ls1021a_drvdata = { - .pm_support = false, + .pm_support = true, + .scfg_support = true, + .ops = &ls1021a_pcie_host_ops, + .exit_from_l2 = ls1021a_pcie_exit_from_l2, }; static const struct ls_pcie_drvdata layerscape_drvdata = { .pf_off = 0xc0000, .pm_support = true, + .ops = &ls_pcie_host_ops, .exit_from_l2 = ls_pcie_exit_from_l2, }; @@ -205,6 +267,8 @@ static int ls_pcie_probe(struct platform_device *pdev) struct dw_pcie *pci; struct ls_pcie *pcie; struct resource *dbi_base; + u32 index[2]; + int ret; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) @@ -217,9 +281,8 @@ static int ls_pcie_probe(struct platform_device *pdev) pcie->drvdata = of_device_get_match_data(dev); pci->dev = dev; - pci->pp.ops = &ls_pcie_host_ops; - pcie->pci = pci; + pci->pp.ops = pcie->drvdata->ops; dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base); @@ -230,6 +293,20 @@ static int ls_pcie_probe(struct platform_device *pdev) pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off; + if (pcie->drvdata->scfg_support) { + pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg"); + if (IS_ERR(pcie->scfg)) { + dev_err(dev, "No syscfg phandle specified\n"); + return PTR_ERR(pcie->scfg); + } + + ret = of_property_read_u32_array(dev->of_node, "fsl,pcie-scfg", index, 2); + if (ret) + return ret; + + pcie->index = index[1]; + } + if (!ls_pcie_is_bridge(pcie)) return -ENODEV;