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Wed, 18 Oct 2023 16:38:08 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F01FB20049; Wed, 18 Oct 2023 16:38:05 +0000 (GMT) Received: from sapthagiri.in.ibm.com (unknown [9.43.47.66]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 18 Oct 2023 16:38:05 +0000 (GMT) From: Srikar Dronamraju To: Michael Ellerman Subject: [PATCH v2 1/6] powerpc/smp: Cache CPU has Asymmetric SMP Date: Wed, 18 Oct 2023 22:07:41 +0530 Message-ID: <20231018163751.2423181-2-srikar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231018163751.2423181-1-srikar@linux.vnet.ibm.com> References: <20231018163751.2423181-1-srikar@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 6vLPCBCAxijA96s6UPL7XrT1zS9Gylz2 X-Proofpoint-ORIG-GUID: YZNut4nXH1nZZFaLtI_YCW8a6lgS7Dni X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-18_15,2023-10-18_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 malwarescore=0 mlxlogscore=999 suspectscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2310180138 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Valentin Schneider , Srikar Dronamraju , Peter Zijlstra , "ndesaulniers@google.com" , linux-kernel@vger.kernel.org, Rohan McLure , Nicholas Piggin , linuxppc-dev , Josh Poimboeuf Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Currently cpu feature flag is checked whenever powerpc_smt_flags gets called. This is an unnecessary overhead. CPU_FTR_ASYM_SMT is set based on the processor and all processors will either have this set or will have it unset. Hence only check for the feature flag once and cache it to be used subsequently. This commit will help avoid a branch in powerpc_smt_flags Signed-off-by: Srikar Dronamraju --- Changelog: v1->v2: Using static keys instead of a variable. Using pr_info_once instead of printk arch/powerpc/kernel/smp.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index 5826f5108a12..37c41297c9ce 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -988,18 +988,16 @@ static int __init init_thread_group_cache_map(int cpu, int cache_property) } static bool shared_caches; +DEFINE_STATIC_KEY_FALSE(powerpc_asym_packing); #ifdef CONFIG_SCHED_SMT /* cpumask of CPUs with asymmetric SMT dependency */ static int powerpc_smt_flags(void) { - int flags = SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES; + if (static_branch_unlikely(&powerpc_asym_packing)) + return SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES | SD_ASYM_PACKING; - if (cpu_has_feature(CPU_FTR_ASYM_SMT)) { - printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n"); - flags |= SD_ASYM_PACKING; - } - return flags; + return SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES; } #endif @@ -1686,6 +1684,11 @@ static void __init fixup_topology(void) { int i; + if (cpu_has_feature(CPU_FTR_ASYM_SMT)) { + pr_info_once("Enabling Asymmetric SMT scheduling\n"); + static_branch_enable(&powerpc_asym_packing); + } + #ifdef CONFIG_SCHED_SMT if (has_big_cores) { pr_info("Big cores detected but using small core scheduling\n");