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Mon, 9 Oct 2023 05:54:23 +0000 (GMT) Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 949E920040; Mon, 9 Oct 2023 05:54:22 +0000 (GMT) Received: from ozlabs.au.ibm.com (unknown [9.192.253.14]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 9 Oct 2023 05:54:22 +0000 (GMT) Received: from bgray-lenovo-p15.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id AB61A60531; Mon, 9 Oct 2023 16:54:20 +1100 (AEDT) From: Benjamin Gray To: linuxppc-dev@lists.ozlabs.org Subject: [RFC PATCH 2/6] powerpc/dexcr: Add thread specific DEXCR configuration Date: Mon, 9 Oct 2023 16:54:02 +1100 Message-ID: <20231009055406.142940-3-bgray@linux.ibm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231009055406.142940-1-bgray@linux.ibm.com> References: <20231009055406.142940-1-bgray@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: VOhBoizrpCCLUULDqQbFVfWiU0ufXVTT X-Proofpoint-GUID: q1LUQcsdUk8PFmGp97vyFh58EywwPv3y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-09_04,2023-10-06_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 mlxlogscore=958 mlxscore=0 bulkscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 adultscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2310090051 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ajd@linux.ibm.com, npiggin@gmail.com, Benjamin Gray Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Add capability to track a DEXCR value per thread. Nothing actually changes these values yet, but they are correctly tracked, propagated, and used to set the hardware register. Signed-off-by: Benjamin Gray --- arch/powerpc/include/asm/processor.h | 12 ++++++++++++ arch/powerpc/kernel/process.c | 24 ++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index b2c51d337e60..28a72023f9bd 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -260,6 +260,9 @@ struct thread_struct { unsigned long sier2; unsigned long sier3; unsigned long hashkeyr; + unsigned int dexcr; /* Temporary value saved during thread switch */ + unsigned int dexcr_enabled; /* Bitmask of aspects enabled by this thread */ + unsigned int dexcr_inherit; /* Bitmask of aspects to inherit across exec */ #endif }; @@ -448,6 +451,15 @@ int exit_vmx_usercopy(void); int enter_vmx_ops(void); void *exit_vmx_ops(void *dest); +static inline unsigned long get_thread_dexcr(struct thread_struct const *thread) +{ +#ifdef CONFIG_PPC_BOOK3S_64 + return thread->dexcr_enabled; +#else + return 0; +#endif +} + #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ #endif /* _ASM_POWERPC_PROCESSOR_H */ diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index b68898ac07e1..c05d58b7c6b3 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -1185,6 +1185,9 @@ static inline void save_sprs(struct thread_struct *t) if (cpu_has_feature(CPU_FTR_DEXCR_NPHIE)) t->hashkeyr = mfspr(SPRN_HASHKEYR); + + if (cpu_has_feature(CPU_FTR_ARCH_31)) + t->dexcr = mfspr(SPRN_DEXCR); #endif } @@ -1267,6 +1270,10 @@ static inline void restore_sprs(struct thread_struct *old_thread, if (cpu_has_feature(CPU_FTR_DEXCR_NPHIE) && old_thread->hashkeyr != new_thread->hashkeyr) mtspr(SPRN_HASHKEYR, new_thread->hashkeyr); + + if (cpu_has_feature(CPU_FTR_ARCH_31) && + old_thread->dexcr != get_thread_dexcr(new_thread)) + mtspr(SPRN_DEXCR, get_thread_dexcr(new_thread)); #endif } @@ -1634,6 +1641,11 @@ void arch_setup_new_exec(void) current->thread.regs->amr = default_amr; current->thread.regs->iamr = default_iamr; #endif + +#ifdef CONFIG_PPC_BOOK3S_64 + current->thread.dexcr_enabled &= current->thread.dexcr_inherit; + current->thread.dexcr_enabled |= ~current->thread.dexcr_inherit & DEXCR_INIT; +#endif } #ifdef CONFIG_PPC64 @@ -1878,6 +1890,11 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) #ifdef CONFIG_PPC_BOOK3S_64 if (cpu_has_feature(CPU_FTR_DEXCR_NPHIE)) p->thread.hashkeyr = current->thread.hashkeyr; + + if (cpu_has_feature(CPU_FTR_ARCH_31)) { + p->thread.dexcr_enabled = current->thread.dexcr_enabled; + p->thread.dexcr_inherit = current->thread.dexcr_inherit; + } #endif return 0; } @@ -2000,6 +2017,13 @@ void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) current->thread.hashkeyr = get_random_long(); mtspr(SPRN_HASHKEYR, current->thread.hashkeyr); } + + if (cpu_has_feature(CPU_FTR_ARCH_31)) { + current->thread.dexcr = 0; + current->thread.dexcr_enabled = DEXCR_INIT; + current->thread.dexcr_inherit = 0; + mtspr(SPRN_DEXCR, get_thread_dexcr(¤t->thread)); + } #endif /* CONFIG_PPC_BOOK3S_64 */ } EXPORT_SYMBOL(start_thread);