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Wed, 30 Aug 2023 10:53:37 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5C9A820040; Wed, 30 Aug 2023 10:53:33 +0000 (GMT) Received: from saptarishi.in.ibm.com (unknown [9.43.8.96]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 30 Aug 2023 10:53:33 +0000 (GMT) From: Srikar Dronamraju To: Michael Ellerman Subject: [PATCH 3/4] powerpc/smp: Enable Asym packing for cores on shared processor Date: Wed, 30 Aug 2023 16:22:43 +0530 Message-ID: <20230830105244.62477-4-srikar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230830105244.62477-1-srikar@linux.vnet.ibm.com> References: <20230830105244.62477-1-srikar@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: BftQwLdOMDjas-OImbDKJRgwirAi14Fm X-Proofpoint-GUID: 0TVRk970mXoAX8PaiOSvOXwPnnTTfFK- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-29_16,2023-08-29_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 adultscore=0 clxscore=1015 mlxscore=0 bulkscore=0 impostorscore=0 mlxlogscore=999 spamscore=0 malwarescore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2308300098 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Juergen Gross , Nathan Lynch , Valentin Schneider , Srikar Dronamraju , Paul E McKenney , Peter Zijlstra , linux-kernel@vger.kernel.org, virtualization@lists.linux-foundation.org, Nicholas Piggin , linuxppc-dev , Josh Poimboeuf Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" If there are shared processor lpars, underlying Hypervisor can have more virtual cores to handle that actual physical cores. Starting with Power 9, a core has 2 nearly independent thread groups. On a shared processors lpars, it helps to pack threads to lesser number of cores so that the overall system performance and utilization improves. PowerVM schedules at a core level. Hence packing to fewer cores helps. For example: Lets says there are two 8-core Shared lpars that are actually sharing a 8 Core shared physical pool, each running 8 threads each. Then Consolidating 8 threads to 4 cores on each lpar would help them to perform better. To achieve this, enable SD_ASYM_PACKING flag at CACHE, MC and DIE level. Signed-off-by: Srikar Dronamraju --- arch/powerpc/kernel/smp.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index c7d1484ed230..51403640440c 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -1005,7 +1005,12 @@ static int powerpc_smt_flags(void) */ static int powerpc_shared_cache_flags(void) { - return SD_SHARE_PKG_RESOURCES; + return SD_SHARE_PKG_RESOURCES | asym_pack_flag; +} + +static int powerpc_shared_proc_flags(void) +{ + return asym_pack_flag; } /* @@ -1044,8 +1049,8 @@ static struct sched_domain_topology_level powerpc_topology[] = { { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) }, #endif { shared_cache_mask, powerpc_shared_cache_flags, SD_INIT_NAME(CACHE) }, - { cpu_mc_mask, SD_INIT_NAME(MC) }, - { cpu_cpu_mask, SD_INIT_NAME(DIE) }, + { cpu_mc_mask, powerpc_shared_proc_flags, SD_INIT_NAME(MC) }, + { cpu_cpu_mask, powerpc_shared_proc_flags, SD_INIT_NAME(DIE) }, { NULL, }, }; @@ -1671,7 +1676,9 @@ static void __init fixup_topology(void) { int i; - if (cpu_has_feature(CPU_FTR_ASYM_SMT)) { + if (is_shared_processor()) { + asym_pack_flag = SD_ASYM_PACKING; + } else if (cpu_has_feature(CPU_FTR_ASYM_SMT)) { printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n"); asym_pack_flag = SD_ASYM_PACKING; }