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Fri, 09 Jun 2023 03:00:44 -0700 (PDT) From: Nicholas Piggin To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 3/4] powerpc/64s: Use stncisync instruction for smp_wmb() when available Date: Fri, 9 Jun 2023 20:00:25 +1000 Message-Id: <20230609100026.8946-3-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230609100026.8946-1-npiggin@gmail.com> References: <20230609100026.8946-1-npiggin@gmail.com> MIME-Version: 1.0 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicholas Piggin Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" stncisync orders less than lwsync (only cacheable store-store, not load-load or load-store) so it should be as cheap or cheaper. Microbenchmarks with no actual loads to order shows that the basic execution cost is the same on POWER10. Signed-off-by: Nicholas Piggin --- arch/powerpc/include/asm/barrier.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/barrier.h b/arch/powerpc/include/asm/barrier.h index b95b666f0374..f0ff5737b0d8 100644 --- a/arch/powerpc/include/asm/barrier.h +++ b/arch/powerpc/include/asm/barrier.h @@ -6,6 +6,8 @@ #define _ASM_POWERPC_BARRIER_H #include +#include +#include #ifndef __ASSEMBLY__ #include @@ -41,7 +43,12 @@ /* The sub-arch has lwsync */ #if defined(CONFIG_PPC64) || defined(CONFIG_PPC_E500MC) -# define SMPWMB LWSYNC +# define SMPWMB \ + BEGIN_FTR_SECTION; \ + LWSYNC; \ + FTR_SECTION_ELSE; \ + .long PPC_RAW_STNCISYNC(); \ + ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_31) #elif defined(CONFIG_BOOKE) # define SMPWMB mbar #else