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Thu, 30 Mar 2023 05:50:54 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A5A3A2004B; Thu, 30 Mar 2023 05:50:53 +0000 (GMT) Received: from ozlabs.au.ibm.com (unknown [9.192.253.14]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 30 Mar 2023 05:50:53 +0000 (GMT) Received: from bgray-lenovo-p15.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 4C8636047D; Thu, 30 Mar 2023 16:50:48 +1100 (AEDT) From: Benjamin Gray To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH v2 06/12] powerpc/dexcr: Support custom default DEXCR value Date: Thu, 30 Mar 2023 16:50:34 +1100 Message-Id: <20230330055040.434133-7-bgray@linux.ibm.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230330055040.434133-1-bgray@linux.ibm.com> References: <20230330055040.434133-1-bgray@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 6nGk4aK6ShFQb4SPHmjZYiaK0CvmMBtj X-Proofpoint-GUID: cJlmV206viG_Q2mRE-fIoXxpKnJ2bmrO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-30_01,2023-03-28_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 mlxlogscore=931 spamscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 mlxscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303300043 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: npiggin@gmail.com, Benjamin Gray Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Make the DEXCR value configurable at config time. Intentionally don't limit possible values to support future aspects without needing kernel updates. The default config value enables hashst/hashchk in problem state. This should be safe, as generally software needs to request these instructions be included in the first place. Signed-off-by: Benjamin Gray Reviewed-by: Russell Currey --- New in v1 Preface with: I'm note sure on the best place to put the config. I also don't think there's any need to zero out unknown/unsupported bits. Reserved implies they are ignored by the hardware (from my understanding of the ISA). Current P10s boot with all bits set; lsdexcr (later patch) reports uDEXCR: ff000000 (SBHE, IBRTPD, SRAPD, NPHIE, PHIE, unknown) when you try to read it back. Leaving them be also makes it easier to support newer aspects without a kernel update. If arbitrary value support isn't important, it's probably a nicer interface to make each aspect an entry in a menu. Future work may include dynamic DEXCR controls via prctl() and sysfs. The dynamic controls would be able to override this default DEXCR on a per-process basis. A stronger "PPC_ENFORCE_USER_ROP_PROCTETION" config may be required at such a time to prevent dynamically disabling the hash checks. --- arch/powerpc/Kconfig | 14 ++++++++++++++ arch/powerpc/kernel/cpu_setup_power.c | 3 ++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 47017975fc2b..809ae576e19f 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -1035,6 +1035,20 @@ config PPC_MEM_KEYS If unsure, say y. +config PPC_DEXCR_DEFAULT + hex "Default DEXCR value" + default 0x0000000004000000 + depends on PPC_BOOK3S_64 + help + Power10 introduces the Dynamic Execution Control Register (DEXCR) + to provide fine grained control over various speculation and + security capabilities. This is used as the default DEXCR value. + + It is a 64 bit value that splits into 32 bits for supervisor mode + and 32 bits for problem state. The default config value enables + the hashst/hashck instructions in userspace. See the ISA for + specifics of what each bit controls. + config PPC_SECURE_BOOT prompt "Enable secure boot support" bool diff --git a/arch/powerpc/kernel/cpu_setup_power.c b/arch/powerpc/kernel/cpu_setup_power.c index c00721801a1b..814c825a0661 100644 --- a/arch/powerpc/kernel/cpu_setup_power.c +++ b/arch/powerpc/kernel/cpu_setup_power.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -128,7 +129,7 @@ static void init_PMU_ISA31(void) static void init_DEXCR(void) { - mtspr(SPRN_DEXCR, 0); + mtspr(SPRN_DEXCR, CONFIG_PPC_DEXCR_DEFAULT); mtspr(SPRN_HASHKEYR, 0); }