diff mbox series

[v5,1/7] powerpc/64: Add INTERRUPT_SANITIZE_REGISTERS Kconfig

Message ID 20221201071019.1953023-1-rmclure@linux.ibm.com (mailing list archive)
State Accepted
Commit 0e23347f1e0f2b1c98f87a4088231d0d6f59b962
Headers show
Series [v5,1/7] powerpc/64: Add INTERRUPT_SANITIZE_REGISTERS Kconfig | expand

Commit Message

Rohan McLure Dec. 1, 2022, 7:10 a.m. UTC 
Add Kconfig option for enabling clearing of registers on arrival in an
interrupt handler. This reduces the speculation influence of registers
on kernel internals. The option will be consumed by 64-bit systems that
feature speculation and wish to implement this mitigation.

This patch only introduces the Kconfig option, no actual mitigations.

The primary overhead of this mitigation lies in an increased number of
registers that must be saved and restored by interrupt handlers on
Book3S systems. Enable by default on Book3E systems, which prior to
this patch eagerly save and restore register state, meaning that the
mitigation when implemented will have minimal overhead.

Acked-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Rohan McLure <rmclure@linux.ibm.com>
---
Resubmitting patches as their own series after v6 partially merged:
Link: https://lore.kernel.org/all/166488988686.779920.13794870102696416283.b4-ty@ellerman.id.au/t/
---
 arch/powerpc/Kconfig | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Michael Ellerman Dec. 8, 2022, 12:40 p.m. UTC | #1 
On Thu, 1 Dec 2022 18:10:13 +1100, Rohan McLure wrote:
> Add Kconfig option for enabling clearing of registers on arrival in an
> interrupt handler. This reduces the speculation influence of registers
> on kernel internals. The option will be consumed by 64-bit systems that
> feature speculation and wish to implement this mitigation.
> 
> This patch only introduces the Kconfig option, no actual mitigations.
> 
> [...]

Applied to powerpc/next.

[1/7] powerpc/64: Add INTERRUPT_SANITIZE_REGISTERS Kconfig
      https://git.kernel.org/powerpc/c/0e23347f1e0f2b1c98f87a4088231d0d6f59b962
[2/7] powerpc/64: Add interrupt register sanitisation macros
      https://git.kernel.org/powerpc/c/cbf892ba56677b942020d2bc7ca9b79281fa0bcc
[3/7] powerpc/64: Sanitise common exit code for interrupts
      https://git.kernel.org/powerpc/c/75c5d6b1e194c341371639469fcb8691afa0e254
[4/7] powerpc/64s: IOption for MSR stored in r12
      https://git.kernel.org/powerpc/c/2487fd2e6d61b5293eed8ecd25add3cc78593d38
[5/7] powerpc/64s: Zeroise gprs on interrupt routine entry on Book3S
      https://git.kernel.org/powerpc/c/1df45d78b8a89da6544fab5267e8f5da15073d28
[6/7] powerpc/64e: Clear gprs on interrupt routine entry on Book3E
      https://git.kernel.org/powerpc/c/efe1691ac814e4cf3653538b701662cbd905bddc
[7/7] powerpc/64: Sanitise user registers on interrupt in pseries, POWERNV
      https://git.kernel.org/powerpc/c/7cd882df9485988f7d9b3fae04fde4e95a4c7a74

cheers
diff mbox series

Patch

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 4fd4924f6d50..280c797e0f30 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -531,6 +531,15 @@  config HOTPLUG_CPU
 
 	  Say N if you are unsure.
 
+config INTERRUPT_SANITIZE_REGISTERS
+	bool "Clear gprs on interrupt arrival"
+	depends on PPC64 && ARCH_HAS_SYSCALL_WRAPPER
+	default PPC_BOOK3E_64
+	help
+	  Reduce the influence of user register state on interrupt handlers and
+	  syscalls through clearing user state from registers before handling
+	  the exception.
+
 config PPC_QUEUED_SPINLOCKS
 	bool "Queued spinlocks" if EXPERT
 	depends on SMP