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bh=52kde5xILBG915Jw4ygVrAEzLf81koPS/DHe/nkC28c=; b=XmDJ5C1OW2i30Gl908wVwwTY6WKTBPWdAMo2m14herP/aXN+Mvtfs9eYGeykWLcAmX XjhHz4PZZKwe5e6gG7OkRYlt1Y6izr7GhBCsjRrEx3zKddYu7zb0dWpbgwfxQCbKZdQJ C97e3s1z1rzTMjq0XUAMD1H+iDWkA0JlDEksMbUBS/c6bSpEaicGNnPAHmx1cEJNyB/K 6gj1WHgaGdx+tJ74Bo6E+S2B/Fa7TzbBgXdn3o20Z/S1/2cEiPKHwy1APRiUAJoRbhuV Y5w4R/vwVE17Z2dBSnDfWnyKR738mZliuXYkUyny63dhv66q3sJM6FQCiyMqTGs8kwgb zxHQ== X-Gm-Message-State: ACgBeo1wIomrKY8eS5Voi31p4ErG1Cngq6q5HTs/5Lr43lXxGODNa2J1 z0XX7Ry3MiEZlSvSwHPJbO/+lAV8GjM= X-Google-Smtp-Source: AA6agR73Q07dEIE+DoXNAls2kdpXvBf/5dKiTkD67MC/N+IMp1JEQTyBxW9qZvNmrgP/H+bIjHVLCw== X-Received: by 2002:a17:902:e945:b0:16a:1c41:f66 with SMTP id b5-20020a170902e94500b0016a1c410f66mr51459274pll.129.1662444234808; Mon, 05 Sep 2022 23:03:54 -0700 (PDT) Received: from bobo.ibm.com ([124.170.18.239]) by smtp.gmail.com with ESMTPSA id u126-20020a626084000000b005383988ec0fsm8934864pfb.162.2022.09.05.23.03.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Sep 2022 23:03:51 -0700 (PDT) From: Nicholas Piggin To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH v2 2/3] powerpc/64s: Fix irq state management in runlatch functions Date: Tue, 6 Sep 2022 16:03:36 +1000 Message-Id: <20220906060337.3302557-3-npiggin@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220906060337.3302557-1-npiggin@gmail.com> References: <20220906060337.3302557-1-npiggin@gmail.com> MIME-Version: 1.0 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sachin Sant , Nicholas Piggin Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" When irqs are soft-disabled, MSR[EE] is volatile and can change from 1 to 0 asynchronously (if a PACA_IRQ_MUST_HARD_MASK interrupt hits). So it can not be used to check hard IRQ enabled status, except to confirm it is disabled. ppc64_runlatch_o* functions use MSR this way to decide whether to re-enable MSR[EE] after disabling it, which leads to MSR[EE] being enabled when it shouldn't be (when a PACA_IRQ_MUST_HARD_MASK had disabled it between reading the MSR and clearing EE). This has been tolerated in the kernel previously, and it doesn't seem to cause a problem, but it is ugly and unexpected. Fix this by only re-enabling if PACA_IRQ_HARD_DIS was set. Signed-off-by: Nicholas Piggin --- arch/powerpc/include/asm/runlatch.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/include/asm/runlatch.h b/arch/powerpc/include/asm/runlatch.h index cfb390edf7d0..ceb66d761fe1 100644 --- a/arch/powerpc/include/asm/runlatch.h +++ b/arch/powerpc/include/asm/runlatch.h @@ -19,10 +19,9 @@ extern void __ppc64_runlatch_off(void); do { \ if (cpu_has_feature(CPU_FTR_CTRL) && \ test_thread_local_flags(_TLF_RUNLATCH)) { \ - unsigned long msr = mfmsr(); \ __hard_irq_disable(); \ __ppc64_runlatch_off(); \ - if (msr & MSR_EE) \ + if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) \ __hard_irq_enable(); \ } \ } while (0) @@ -31,10 +30,9 @@ extern void __ppc64_runlatch_off(void); do { \ if (cpu_has_feature(CPU_FTR_CTRL) && \ !test_thread_local_flags(_TLF_RUNLATCH)) { \ - unsigned long msr = mfmsr(); \ __hard_irq_disable(); \ __ppc64_runlatch_on(); \ - if (msr & MSR_EE) \ + if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) \ __hard_irq_enable(); \ } \ } while (0)