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Thu, 12 May 2022 07:46:41 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6BC89A4040; Thu, 12 May 2022 07:46:33 +0000 (GMT) Received: from hbathini-workstation.ibm.com.com (unknown [9.211.109.30]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 12 May 2022 07:46:33 +0000 (GMT) From: Hari Bathini To: bpf@vger.kernel.org, linuxppc-dev Subject: [PATCH 5/5] bpf ppc32: Add instructions for atomic_[cmp]xchg Date: Thu, 12 May 2022 13:15:46 +0530 Message-Id: <20220512074546.231616-6-hbathini@linux.ibm.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512074546.231616-1-hbathini@linux.ibm.com> References: <20220512074546.231616-1-hbathini@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: r8QtyRJIHN0NPICWmDmD1c4VvQ9qLDwN X-Proofpoint-ORIG-GUID: DS3bfz7Bz7Ook08vLsStW7dHE20VY3uT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-11_07,2022-05-12_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 impostorscore=0 mlxscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 lowpriorityscore=0 bulkscore=0 malwarescore=0 spamscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2205120034 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Song Liu , Daniel Borkmann , John Fastabend , Alexei Starovoitov , Andrii Nakryiko , netdev@vger.kernel.org, Paul Mackerras , "Naveen N. Rao" , Yonghong Song , KP Singh , Jordan Niethe , Martin KaFai Lau Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" This adds two atomic opcodes BPF_XCHG and BPF_CMPXCHG on ppc32, both of which include the BPF_FETCH flag. The kernel's atomic_cmpxchg operation fundamentally has 3 operands, but we only have two register fields. Therefore the operand we compare against (the kernel's API calls it 'old') is hard-coded to be BPF_REG_R0. Also, kernel's atomic_cmpxchg returns the previous value at dst_reg + off. JIT the same for BPF too with return value put in BPF_REG_0. BPF_REG_R0 = atomic_cmpxchg(dst_reg + off, BPF_REG_R0, src_reg); Signed-off-by: Hari Bathini --- arch/powerpc/net/bpf_jit_comp32.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/powerpc/net/bpf_jit_comp32.c b/arch/powerpc/net/bpf_jit_comp32.c index 5604ae1b60ab..4690fd6e9e52 100644 --- a/arch/powerpc/net/bpf_jit_comp32.c +++ b/arch/powerpc/net/bpf_jit_comp32.c @@ -829,6 +829,23 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * /* we're done if this succeeded */ PPC_BCC_SHORT(COND_NE, tmp_idx); break; + case BPF_CMPXCHG: + /* Compare with old value in BPF_REG_0 */ + EMIT(PPC_RAW_CMPW(bpf_to_ppc(BPF_REG_0), _R0)); + /* Don't set if different from old value */ + PPC_BCC_SHORT(COND_NE, (ctx->idx + 3) * 4); + fallthrough; + case BPF_XCHG: + /* store new value */ + EMIT(PPC_RAW_STWCX(src_reg, tmp_reg, dst_reg)); + PPC_BCC_SHORT(COND_NE, tmp_idx); + /* + * Return old value in src_reg for BPF_XCHG & + * BPF_REG_0 for BPF_CMPXCHG. + */ + EMIT(PPC_RAW_MR(imm == BPF_XCHG ? src_reg : bpf_to_ppc(BPF_REG_0), + _R0)); + break; default: pr_err_ratelimited("eBPF filter atomic op code %02x (@%d) unsupported\n", code, i);