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[61.68.211.196]) by smtp.gmail.com with ESMTPSA id q14-20020a056a00150e00b004f741b5c071sm541737pfu.86.2022.03.08.05.51.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Mar 2022 05:51:13 -0800 (PST) From: Nicholas Piggin To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 06/14] powerpc/rtas: Load rtas entry MSR explicitly Date: Tue, 8 Mar 2022 23:50:39 +1000 Message-Id: <20220308135047.478297-7-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20220308135047.478297-1-npiggin@gmail.com> References: <20220308135047.478297-1-npiggin@gmail.com> MIME-Version: 1.0 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Dufour , Nicholas Piggin Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Rather than adjust the current MSR value to find the rtas entry MSR on 64-bit, load the explicit value we want as 32-bit does. This prevents some facilities (e.g., VEC and VSX) from being left enabled which doesn't seem to cause a problem but it's more consistent to always use the same MSR and minimise facilities enabled. Signed-off-by: Nicholas Piggin Reviewed-by: Laurent Dufour --- arch/powerpc/kernel/rtas_entry.S | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/arch/powerpc/kernel/rtas_entry.S b/arch/powerpc/kernel/rtas_entry.S index 7b93687b9a10..08eb731f08b8 100644 --- a/arch/powerpc/kernel/rtas_entry.S +++ b/arch/powerpc/kernel/rtas_entry.S @@ -99,14 +99,7 @@ _GLOBAL(enter_rtas) clrldi r4,r4,2 /* convert to realmode address */ mtlr r4 - li r0,0 - ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI - andc r0,r6,r0 - - li r9,1 - rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG) - ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE - andc r6,r0,r9 + LOAD_REG_IMMEDIATE(r6, MSR_ME) __enter_rtas: LOAD_REG_ADDR(r4, rtas)