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[61.68.211.196]) by smtp.gmail.com with ESMTPSA id q14-20020a056a00150e00b004f741b5c071sm541737pfu.86.2022.03.08.05.51.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Mar 2022 05:51:10 -0800 (PST) From: Nicholas Piggin To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 05/14] powerpc/rtas: Modernise RI clearing on 64-bit Date: Tue, 8 Mar 2022 23:50:38 +1000 Message-Id: <20220308135047.478297-6-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20220308135047.478297-1-npiggin@gmail.com> References: <20220308135047.478297-1-npiggin@gmail.com> MIME-Version: 1.0 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Dufour , Nicholas Piggin Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" mtmsrd L=1 can clear MSR[RI] without the previous MSR value; it does not require sync; it can be moved later to before SRRs are live. Signed-off-by: Nicholas Piggin Reviewed-by: Laurent Dufour --- arch/powerpc/kernel/rtas_entry.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/kernel/rtas_entry.S b/arch/powerpc/kernel/rtas_entry.S index 45fa661c2ff6..7b93687b9a10 100644 --- a/arch/powerpc/kernel/rtas_entry.S +++ b/arch/powerpc/kernel/rtas_entry.S @@ -109,13 +109,13 @@ _GLOBAL(enter_rtas) andc r6,r0,r9 __enter_rtas: - sync /* disable RI so SRR0/1 */ - mtmsrd r0 /* don't get trashed */ - LOAD_REG_ADDR(r4, rtas) ld r5,RTASENTRY(r4) /* get the rtas->entry value */ ld r4,RTASBASE(r4) /* get the rtas->base value */ + li r0,0 + mtmsrd r0,1 /* disable RI before using SRR0/1 */ + mtspr SPRN_SRR0,r5 mtspr SPRN_SRR1,r6 RFI_TO_KERNEL