diff mbox series

soc: fsl: qe: Fix typo in a comment

Message ID 20211113055900.212568-1-wangborong@cdjrlc.com (mailing list archive)
State Handled Elsewhere, archived
Headers show
Series soc: fsl: qe: Fix typo in a comment | expand

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Commit Message

Jason Wang Nov. 13, 2021, 5:59 a.m. UTC
The double `is' in a comment is repeated, thus one of them
should be removed.

Signed-off-by: Jason Wang <wangborong@cdjrlc.com>
---
 drivers/soc/fsl/qe/qe.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Christophe Leroy Nov. 15, 2021, 8:06 a.m. UTC | #1
Le 13/11/2021 à 06:59, Jason Wang a écrit :
> The double `is' in a comment is repeated, thus one of them
> should be removed.

You are also clean blanks it seems, so say it or don't do it.

> 
> Signed-off-by: Jason Wang <wangborong@cdjrlc.com>
> ---
>   drivers/soc/fsl/qe/qe.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
> index 4d38c80f8be8..b3c226eb5292 100644
> --- a/drivers/soc/fsl/qe/qe.c
> +++ b/drivers/soc/fsl/qe/qe.c
> @@ -147,7 +147,7 @@ EXPORT_SYMBOL(qe_issue_cmd);
>    * memory mapped space.
>    * The BRG clock is the QE clock divided by 2.
>    * It was set up long ago during the initial boot phase and is
> - * is given to us.
> + * given to us.
>    * Baud rate clocks are zero-based in the driver code (as that maps
>    * to port numbers). Documentation uses 1-based numbering.
>    */
> @@ -421,7 +421,7 @@ static void qe_upload_microcode(const void *base,
>   
>   	for (i = 0; i < be32_to_cpu(ucode->count); i++)
>   		iowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);
> -	
> +

This change is not linked to the double "is".

>   	/* Set I-RAM Ready Register */
>   	iowrite32be(QE_IRAM_READY, &qe_immr->iram.iready);
>   }
>
diff mbox series

Patch

diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 4d38c80f8be8..b3c226eb5292 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -147,7 +147,7 @@  EXPORT_SYMBOL(qe_issue_cmd);
  * memory mapped space.
  * The BRG clock is the QE clock divided by 2.
  * It was set up long ago during the initial boot phase and is
- * is given to us.
+ * given to us.
  * Baud rate clocks are zero-based in the driver code (as that maps
  * to port numbers). Documentation uses 1-based numbering.
  */
@@ -421,7 +421,7 @@  static void qe_upload_microcode(const void *base,
 
 	for (i = 0; i < be32_to_cpu(ucode->count); i++)
 		iowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);
-	
+
 	/* Set I-RAM Ready Register */
 	iowrite32be(QE_IRAM_READY, &qe_immr->iram.iready);
 }