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Sat, 4 Sep 2021 06:50:03 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F00A64C040; Sat, 4 Sep 2021 06:49:54 +0000 (GMT) Received: from localhost.localdomain.com (unknown [9.43.55.112]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Sat, 4 Sep 2021 06:49:54 +0000 (GMT) From: Kajol Jain To: mpe@ellerman.id.au, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, jolsa@kernel.org, namhyung@kernel.org, linux-perf-users@vger.kernel.org, ak@linux.intel.com Subject: [PATCH 1/3] perf: Add macros to specify onchip L2/L3 accesses Date: Sat, 4 Sep 2021 12:19:30 +0530 Message-Id: <20210904064932.307610-1-kjain@linux.ibm.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: L6NsZ3BWVeszSLtJ59a0Zd1PCgBqs-WZ X-Proofpoint-ORIG-GUID: 6QXnz4B6sKpuGnC80-emFXhP8oY3eGB_ X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-09-04_02:2021-09-03, 2021-09-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 mlxlogscore=999 mlxscore=0 phishscore=0 adultscore=0 clxscore=1011 lowpriorityscore=0 spamscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2108310000 definitions=main-2109040044 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, songliubraving@fb.com, atrajeev@linux.vnet.ibm.com, daniel@iogearbox.net, rnsastry@linux.ibm.com, alexander.shishkin@linux.intel.com, kjain@linux.ibm.com, ast@kernel.org, yao.jin@linux.intel.com, maddy@linux.ibm.com, paulus@samba.org, kan.liang@linux.intel.com Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Add couple of new macros to represent onchip L2 and onchip L3 accesses. Signed-off-by: Kajol Jain --- include/uapi/linux/perf_event.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h index f92880a15645..030b3e990ac3 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -1265,7 +1265,9 @@ union perf_mem_data_src { #define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ -/* 5-0xa available */ +#define PERF_MEM_LVLNUM_OC_L2 0x05 /* On Chip L2 */ +#define PERF_MEM_LVLNUM_OC_L3 0x06 /* On Chip L3 */ +/* 7-0xa available */ #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ #define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */ #define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */