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[75.142.250.213]) by smtp.gmail.com with ESMTPSA id x199sm1954310oif.5.2021.06.08.14.24.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Jun 2021 14:24:08 -0700 (PDT) From: trix@redhat.com To: mdf@kernel.org, robh+dt@kernel.org, hao.wu@intel.com, corbet@lwn.net, fbarrat@linux.ibm.com, ajd@linux.ibm.com, bbrezillon@kernel.org, arno@natisbad.org, schalla@marvell.com, herbert@gondor.apana.org.au, davem@davemloft.net, gregkh@linuxfoundation.org, Sven.Auhagen@voleatech.de, grandmaster@al2klimov.de Subject: [PATCH 03/11] Documentation: ocxl.rst: change FPGA indirect article to an Date: Tue, 8 Jun 2021 14:23:42 -0700 Message-Id: <20210608212350.3029742-5-trix@redhat.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210608212350.3029742-1-trix@redhat.com> References: <20210608212350.3029742-1-trix@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=trix@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Tom Rix , linux-fpga@vger.kernel.org, linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Tom Rix Change use of 'a fpga' to 'an fpga' Signed-off-by: Tom Rix Acked-by: Andrew Donnellan --- Documentation/userspace-api/accelerators/ocxl.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/userspace-api/accelerators/ocxl.rst b/Documentation/userspace-api/accelerators/ocxl.rst index 14cefc020e2d5..db7570d5e50d1 100644 --- a/Documentation/userspace-api/accelerators/ocxl.rst +++ b/Documentation/userspace-api/accelerators/ocxl.rst @@ -6,7 +6,7 @@ OpenCAPI is an interface between processors and accelerators. It aims at being low-latency and high-bandwidth. The specification is developed by the `OpenCAPI Consortium `_. -It allows an accelerator (which could be a FPGA, ASICs, ...) to access +It allows an accelerator (which could be an FPGA, ASICs, ...) to access the host memory coherently, using virtual addresses. An OpenCAPI device can also host its own memory, that can be accessed from the host.