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Thu, 19 Nov 2020 05:41:42 +0000 (GMT) Received: from fir03.in.ibm.com (unknown [9.121.59.65]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 19 Nov 2020 05:41:41 +0000 (GMT) From: Sandipan Das To: mpe@ellerman.id.au Subject: [PATCH 2/2] powerpc: sstep: Fix store and update instructions Date: Thu, 19 Nov 2020 11:11:39 +0530 Message-Id: <20201119054139.244083-2-sandipan@linux.ibm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201119054139.244083-1-sandipan@linux.ibm.com> References: <20201119054139.244083-1-sandipan@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-19_01:2020-11-17, 2020-11-19 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 mlxlogscore=873 impostorscore=0 malwarescore=0 phishscore=0 adultscore=0 lowpriorityscore=0 suspectscore=1 spamscore=0 bulkscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2011190037 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ravi.bangoria@linux.ibm.com, jniethe5@gmail.com, paulus@samba.org, naveen.n.rao@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org, dja@axtens.net Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The Power ISA says that the fixed-point store and update instructions must not use R0 for the base address (RA). In this case, the instruction is invalid. This applies to the following instructions. * Store Byte with Update (stbu) * Store Byte with Update Indexed (stbux) * Store Halfword with Update (sthu) * Store Halfword with Update Indexed (sthux) * Store Word with Update (stwu) * Store Word with Update Indexed (stwux) * Store Doubleword with Update (stdu) * Store Doubleword with Update Indexed (stdux) To remove any inconsistencies, this adds an additional check for the aforementioned instructions to make sure that they are treated as unknown by the emulation infrastructure when RA = 0. The kernel will then fallback to executing the instruction on hardware. Signed-off-by: Sandipan Das --- arch/powerpc/lib/sstep.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c index 25a5436be6c6..1c20c14f8757 100644 --- a/arch/powerpc/lib/sstep.c +++ b/arch/powerpc/lib/sstep.c @@ -2226,17 +2226,23 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, case 149: /* stdx */ case 181: /* stdux */ + if (u && ra == 0) + return -1; op->type = MKOP(STORE, u, 8); break; #endif case 151: /* stwx */ case 183: /* stwux */ + if (u && ra == 0) + return -1; op->type = MKOP(STORE, u, 4); break; case 215: /* stbx */ case 247: /* stbux */ + if (u && ra == 0) + return -1; op->type = MKOP(STORE, u, 1); break; @@ -2265,6 +2271,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, case 407: /* sthx */ case 439: /* sthux */ + if (u && ra == 0) + return -1; op->type = MKOP(STORE, u, 2); break; @@ -2568,12 +2576,16 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, case 36: /* stw */ case 37: /* stwu */ + if (u && ra == 0) + return -1; op->type = MKOP(STORE, u, 4); op->ea = dform_ea(word, regs); break; case 38: /* stb */ case 39: /* stbu */ + if (u && ra == 0) + return -1; op->type = MKOP(STORE, u, 1); op->ea = dform_ea(word, regs); break; @@ -2596,6 +2608,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, case 44: /* sth */ case 45: /* sthu */ + if (u && ra == 0) + return -1; op->type = MKOP(STORE, u, 2); op->ea = dform_ea(word, regs); break; @@ -2746,6 +2760,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, op->type = MKOP(STORE, 0, 8); break; case 1: /* stdu */ + if (ra == 0) + return -1; op->type = MKOP(STORE, UPDATE, 8); break; case 2: /* stq */