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Wed, 22 Jul 2020 10:24:43 -0700 (PDT) Received: from localhost.localdomain ([188.25.219.134]) by smtp.gmail.com with ESMTPSA id bt26sm311517edb.17.2020.07.22.10.24.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 10:24:43 -0700 (PDT) From: Vladimir Oltean To: robh+dt@kernel.org, shawnguo@kernel.org, mpe@ellerman.id.au, devicetree@vger.kernel.org Subject: [PATCH devicetree 3/4] powerpc: dts: t1040rdb: put SGMII PHY under &mdio0 label Date: Wed, 22 Jul 2020 20:24:21 +0300 Message-Id: <20200722172422.2590489-4-olteanv@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200722172422.2590489-1-olteanv@gmail.com> References: <20200722172422.2590489-1-olteanv@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Thu, 23 Jul 2020 08:08:49 +1000 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: madalin.bucur@oss.nxp.com, linux-kernel@vger.kernel.org, radu-andrei.bulie@nxp.com, fido_max@inbox.ru, paulus@samba.org, netdev@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" We're going to add 8 more PHYs in a future patch. It is easier to follow the hardware description if we don't need to fish for the path of the MDIO controllers inside the SoC and just use the labels. Signed-off-by: Vladimir Oltean --- arch/powerpc/boot/dts/fsl/t1040rdb.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/boot/dts/fsl/t1040rdb.dts b/arch/powerpc/boot/dts/fsl/t1040rdb.dts index 65ff34c49025..40d7126dbe90 100644 --- a/arch/powerpc/boot/dts/fsl/t1040rdb.dts +++ b/arch/powerpc/boot/dts/fsl/t1040rdb.dts @@ -59,12 +59,6 @@ ethernet@e4000 { phy-handle = <&phy_sgmii_2>; phy-connection-type = "sgmii"; }; - - mdio@fc000 { - phy_sgmii_2: ethernet-phy@3 { - reg = <0x03>; - }; - }; }; }; @@ -76,3 +70,9 @@ cpld@3,0 { }; #include "t1040si-post.dtsi" + +&mdio0 { + phy_sgmii_2: ethernet-phy@3 { + reg = <0x3>; + }; +};