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DIR:OUT; SFP:1102; SCL:1; SRVR:VI1PR10MB1950; H:VI1PR10MB2672.EURPRD10.PROD.OUTLOOK.COM; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: prevas.se does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: iY4V8mvoG5SJUI2Hu3/s4cR0ATbU25JjUJY87KCD/Z579idi+L4su6UuQ0Cx3iZODFEeMuECo4maI3ZfHIyrJnmttEnuRsSHUAzbT39sJfeX7Dvvo7N4B232GHOS1clZL4swA7snUAwX8llmHp8IYB+emPUL2C2OeisZsAxIoxg+GtqS7hUylSRUfSykKE3MB1iGBhXQxSyrEph5UX5uR4z1C8ACgChCvQ7p6XEQChZe0kkhMDyqO2YRHcy2XivFCNkrU+CAE4p2MfvUKoLXRgyVxKtFIV4nK4Pn3o7g4s5ao9WpXTVb0w5HA1yMWjLCULwusRRL7et4ErbpE0yoGtA9sgAm5HC+T/f0skwfS64/HUW6tSoW+dUDXmCuIhXBLLWezoZjYGut9AGVmzFA6bptD2hXVnT8YjoL95EAmtU= MIME-Version: 1.0 X-OriginatorOrg: prevas.dk X-MS-Exchange-CrossTenant-Network-Message-Id: 2ae9f9da-f716-49b5-d22d-08d6d7943c4a X-MS-Exchange-CrossTenant-originalarrivaltime: 13 May 2019 11:14:58.8953 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d350cf71-778d-4780-88f5-071a4cb1ed61 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR10MB1950 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , "linux-kernel@vger.kernel.org" , Scott Wood , Rasmus Villemoes , Rob Herring , "linuxppc-dev@lists.ozlabs.org" , "linux-arm-kernel@lists.infradead.org" Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Reading table 4-30, and its footnotes, of the QUICC Engine Block Reference Manual shows that the set of snum _values_ is not necessarily just a function of the _number_ of snums, as given in the fsl,qe-num-snums property. As an alternative, to make it easier to add support for other variants of the QUICC engine IP, this introduces a new binding fsl,qe-snums, which automatically encodes both the number of snums and the actual values to use. Signed-off-by: Rasmus Villemoes Reviewed-by: Rob Herring --- Rob, thanks for the review of v2. However, since I moved the example from the commit log to the binding (per Joakim's request), I didn't add a Reviewed-by tag for this revision. .../devicetree/bindings/soc/fsl/cpm_qe/qe.txt | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt index d7afaff5faff..05ec2a838c54 100644 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt @@ -18,7 +18,8 @@ Required properties: - reg : offset and length of the device registers. - bus-frequency : the clock frequency for QUICC Engine. - fsl,qe-num-riscs: define how many RISC engines the QE has. -- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use for the +- fsl,qe-snums: This property has to be specified as '/bits/ 8' value, + defining the array of serial number (SNUM) values for the virtual threads. Optional properties: @@ -34,6 +35,11 @@ Recommended properties - brg-frequency : the internal clock source frequency for baud-rate generators in Hz. +Deprecated properties +- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use + for the threads. Use fsl,qe-snums instead to not only specify the + number of snums, but also their values. + Example: qe@e0100000 { #address-cells = <1>; @@ -44,6 +50,11 @@ Example: reg = ; brg-frequency = <0>; bus-frequency = <179A7B00>; + fsl,qe-snums = /bits/ 8 < + 0x04 0x05 0x0C 0x0D 0x14 0x15 0x1C 0x1D + 0x24 0x25 0x2C 0x2D 0x34 0x35 0x88 0x89 + 0x98 0x99 0xA8 0xA9 0xB8 0xB9 0xC8 0xC9 + 0xD8 0xD9 0xE8 0xE9>; } * Multi-User RAM (MURAM)