From patchwork Tue Apr 30 13:36:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rasmus Villemoes X-Patchwork-Id: 1093378 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44tnWN3jnyz9s47 for ; Wed, 1 May 2019 02:47:28 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=prevas.dk Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=prevas.se header.i=@prevas.se header.b="iL3toJ5Z"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44tnWN2VjfzDqVB for ; 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DIR:OUT; SFP:1102; SCL:1; SRVR:VI1PR10MB0735; H:VI1PR10MB2672.EURPRD10.PROD.OUTLOOK.COM; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: prevas.se does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: +U02E9WoIVtOiHzYRRORe2YnVu1SS4BWueGXCxA1AqOSLAM2KfX1b6RvQFF16GXSe6hxlp2K/cpXWG9KkWgeo+aIKh4570AjJuKhMFWDgxzVk+JRTOomi/doY87Q49Ps9oP0NzK6r+5AuExyFTrPJonmMpLieG2ai+HlJVLMq8sowgJFF39JJyoXHGTPhN94sZRBYhjbPRPAUeZDfASmfdVvfQO/mwgu9zYEvogdHvn69iHUrFiJIPFJ3VE+NY9viVlhIw659Qsgx76xqhKCjsGI837vi/HaITpxlemMVNrp0gQyOMQRhtEXR87Ah6sP2V9HmGKFd4xEmJpsAE7EH1XbZzLp46+UNWUO7MKuNrsNicB9MvPfSDauGRO4FGXHMszlvzqikKOyabFvmzOzrS4DKYGfFTdvU4q2vV8UdbY= MIME-Version: 1.0 X-OriginatorOrg: prevas.dk X-MS-Exchange-CrossTenant-Network-Message-Id: 80a6e09c-05d1-4323-12b5-08d6cd70dc17 X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Apr 2019 13:36:33.5066 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d350cf71-778d-4780-88f5-071a4cb1ed61 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR10MB0735 X-Mailman-Approved-At: Wed, 01 May 2019 02:38:35 +1000 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Valentin Longchamp , "linux-kernel@vger.kernel.org" , Scott Wood , Rasmus Villemoes , Rob Herring , "linuxppc-dev@lists.ozlabs.org" , "linux-arm-kernel@lists.infradead.org" Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The current code assumes that the set of snum _values_ to populate the snums[] array with is a function of the _number_ of snums alone. However, reading table 4-30, and its footnotes, of the QUICC Engine Block Reference Manual shows that that is a bit too naive. As an alternative, this introduces a new binding fsl,qe-snums, which automatically encodes both the number of snums and the actual values to use. Conveniently, of_property_read_variable_u8_array does exactly what we need. For example, for the MPC8309, one would specify the property as fsl,qe-snums = /bits/ 8 < 0x88 0x89 0x98 0x99 0xa8 0xa9 0xb8 0xb9 0xc8 0xc9 0xd8 0xd9 0xe8 0xe9>; Signed-off-by: Rasmus Villemoes --- .../devicetree/bindings/soc/fsl/cpm_qe/qe.txt | 8 +++++++- drivers/soc/fsl/qe/qe.c | 14 +++++++++++++- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt index d7afaff5faff..05f5f485562a 100644 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt @@ -18,7 +18,8 @@ Required properties: - reg : offset and length of the device registers. - bus-frequency : the clock frequency for QUICC Engine. - fsl,qe-num-riscs: define how many RISC engines the QE has. -- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use for the +- fsl,qe-snums: This property has to be specified as '/bits/ 8' value, + defining the array of serial number (SNUM) values for the virtual threads. Optional properties: @@ -34,6 +35,11 @@ Recommended properties - brg-frequency : the internal clock source frequency for baud-rate generators in Hz. +Deprecated properties +- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use + for the threads. Use fsl,qe-snums instead to not only specify the + number of snums, but also their values. + Example: qe@e0100000 { #address-cells = <1>; diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index aff9d1373529..af3c2b2b268f 100644 --- a/drivers/soc/fsl/qe/qe.c +++ b/drivers/soc/fsl/qe/qe.c @@ -283,7 +283,6 @@ EXPORT_SYMBOL(qe_clock_source); */ static void qe_snums_init(void) { - int i; static const u8 snum_init_76[] = { 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D, 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89, @@ -304,9 +303,22 @@ static void qe_snums_init(void) 0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59, 0x68, 0x69, 0x78, 0x79, 0x80, 0x81, }; + struct device_node *qe; const u8 *snum_init; + int i; bitmap_zero(snum_state, QE_NUM_OF_SNUM); + qe = qe_get_device_node(); + if (qe) { + i = of_property_read_variable_u8_array(qe, "fsl,qe-snums", + snums, 1, QE_NUM_OF_SNUM); + of_node_put(qe); + if (i > 0) { + qe_num_of_snum = i; + return; + } + } + qe_num_of_snum = qe_get_num_of_snums(); if (qe_num_of_snum == 76)