From patchwork Thu Jun 8 15:36:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 773348 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wk8lc6pF7z9s76 for ; Fri, 9 Jun 2017 01:41:00 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="PYPLoBtQ"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3wk8lc5m11zDqNT for ; Fri, 9 Jun 2017 01:41:00 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="PYPLoBtQ"; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from mail-pf0-x243.google.com (mail-pf0-x243.google.com [IPv6:2607:f8b0:400e:c00::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3wk8fD3Q8RzDqSW for ; Fri, 9 Jun 2017 01:36:20 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="PYPLoBtQ"; dkim-atps=neutral Received: by mail-pf0-x243.google.com with SMTP id f27so5541378pfe.0 for ; Thu, 08 Jun 2017 08:36:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=FvCz1TQkRwjoE0rO+YspHDNA09o1mGMCpTT/rzdNoUM=; b=PYPLoBtQn+P+oQLiVg7R9qK+eXOIhvpSl5bSH2+T5/go5An2L1Fg/rbynuh+YpMzdN D42Wn4lHiBluJQKh3Z3C4TXi13+1puPwM+s4iC6oYUIebhRPPloB4ppazRSrN+5oNS8d S8798MwEtrb4iog25W+ceSvXDdK3JfzjMm3MAPwFWbJerX+XRjUwAfosFvwINkdwK+gh fdUZOuDr5NPj0avTZi1cfUKwPWUaWBi3cMplwVA0i2LlXnuW4/rt8Z/Vy5TlXHl4CA/d 036pDGDL4a1tZT9bGJbiJNQ30BjhtfFgTUps1GX9b7Fhw7OQKyTZvTreTEGGDHFhNtFX Ke4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=FvCz1TQkRwjoE0rO+YspHDNA09o1mGMCpTT/rzdNoUM=; b=g6P/jcetU7Ptc0gbQA0iL3sqf7ccE2YKJTl9ZHnqfRiwXSqP5mhcdFYwPBnH69Uy/N UMGrTkttvNlOFLu+59YMCLWpf3z6xcBQ2UmxIm+V/+f5TqtofgS3qheeFWhh+EUhnRbf RG71ZKtBqyssjkIw3NA5aVfEwH85IsoGHLfAsa+7pz+hBC2WEpFdHtxQEpdsZO6DMJ4F R9011kqsCkc6IzE0AgC4oVwSGGrrO8A7+YEx7KsYISvT1HgRR8TETgb085ITfoWwrOUK 6oSdIBWOsMJgcDfV7jz1J7mPIaiammAEBbqFGFh5umDh8FTzOYP9yxE7mAUomucd1oU7 4ybQ== X-Gm-Message-State: AODbwcCjiXs/W2tjcPn7R99VTFhHjD44FqOxlzFBgAZyLAYIIobyyjYh 24cYH85MNDS/AEfI X-Received: by 10.98.39.2 with SMTP id n2mr26680640pfn.182.1496936178515; Thu, 08 Jun 2017 08:36:18 -0700 (PDT) Received: from roar.au.ibm.com (14-202-185-133.tpgi.com.au. [14.202.185.133]) by smtp.gmail.com with ESMTPSA id q194sm10360445pfq.56.2017.06.08.08.36.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Jun 2017 08:36:17 -0700 (PDT) From: Nicholas Piggin To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 1/4] powerpc/64s: context switch leave interrupts hard enabled for radix Date: Fri, 9 Jun 2017 01:36:06 +1000 Message-Id: <20170608153609.19217-1-npiggin@gmail.com> X-Mailer: git-send-email 2.11.0 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicholas Piggin Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Commit 4387e9ff25 ("[POWERPC] Fix PMU + soft interrupt disable bug") hard disabled interrupts over the low level context switch, because the SLB management can't cope with a PMU interrupt accesing the stack in that window. Radix based kernel mapping does not use the SLB so it does not require interrupts hard disabled here. This is worth 1-2% in context switch performance on POWER9. Signed-off-by: Nicholas Piggin --- arch/powerpc/kernel/entry_64.S | 8 ++++++++ arch/powerpc/kernel/process.c | 14 ++++++++------ 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index 6f70ea821a07..91f9fdc2d027 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S @@ -607,6 +607,14 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT) top of the kernel stack. */ addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE + /* + * PMU interrupts in radix may come in here. They will use r1, not + * PACAKSAVE, so this stack switch will not cause a problem. They + * will store to the process stack, which may then be migrated to + * another CPU. However the rq lock release on this CPU paired with + * the rq lock acquire on the new CPU before the stack becomes + * active on the new CPU, will order those stores. + */ mr r1,r8 /* start using new stack pointer */ std r7,PACAKSAVE(r13) diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index 5cbb8b1faf7e..45faa9a32a01 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -1199,12 +1199,14 @@ struct task_struct *__switch_to(struct task_struct *prev, __switch_to_tm(prev, new); - /* - * We can't take a PMU exception inside _switch() since there is a - * window where the kernel stack SLB and the kernel stack are out - * of sync. Hard disable here. - */ - hard_irq_disable(); + if (!radix_enabled()) { + /* + * We can't take a PMU exception inside _switch() since there + * is a window where the kernel stack SLB and the kernel stack + * are out of sync. Hard disable here. + */ + hard_irq_disable(); + } /* * Call restore_sprs() before calling _switch(). If we move it after