From patchwork Tue Mar 14 12:36:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 738685 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vjDrM5V0Vz9s1h for ; Tue, 14 Mar 2017 23:41:39 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="p83m4QVC"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3vjDrM3vTLzDrDV for ; Tue, 14 Mar 2017 23:41:39 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="p83m4QVC"; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from mail-pg0-x243.google.com (mail-pg0-x243.google.com [IPv6:2607:f8b0:400e:c05::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3vjDl768P0zDr8S for ; Tue, 14 Mar 2017 23:37:07 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="p83m4QVC"; dkim-atps=neutral Received: by mail-pg0-x243.google.com with SMTP id 77so24220249pgc.0 for ; Tue, 14 Mar 2017 05:37:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=za+ubWsZRk5QKG747WT8v1X1bsxCCcRMZQ/mfmwvbZw=; b=p83m4QVCXtjJuYSf1bijKOGjWn1JHbSrh62oYZkvb88ZZT90RwPd9nVRoVeYYbfUR5 WGmJJURi+VnLzVbIePuwq5GaBf7j/cWvHBbCm2mVOmXhAB8cg99t1pLRKJTD5EqEVl8I 0Ql01pESuv5hiqqlyCidIKK0jVfZHAx3VP7KL9I0RP0Xp7eGv0Y+n22pvguENslrLSDK ZP/ceBRhGh+OZ9S342COWNrFJCa7qqOhYIeTRzO9Vz/CydwW0pLyHTXn00LVG3oNvU4C PKaZraITTijznBP/jmNULJNFFhSpywD8gIXL4wdnfIvwndUFK/U0MJFmvVy5CN6gkwTu xpBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=za+ubWsZRk5QKG747WT8v1X1bsxCCcRMZQ/mfmwvbZw=; b=KqQPTU21zLyNGkEpQyYcziQGk+FR1BYbO/JEd2ewGNJpNib28heKA3r7nJTlEADFAu ahErbq4TmtT1us1iULKmfzCZ2ZCwAmbmQaaxTeI8TvTrbhkoaTzhrOtEYUNOMeCVV3ac XsdEPh5LIWZNvJX3r+edmWpdJEJUaFvZpeZAmHvLEOH8Gjj7e9el2BPtSaJUFVdccfRr Smls8xQUFcZA2jtsEO/cPecl2j5EuubaNQxhbPwbUNW8tGAPE6oc5eQ8VdIYSbx3XX5w erdCgdL2W5YPOlJz9muexX1gewQl2X6djVhulAozvLkjXMRi8Hi+jjEFaYCHSHvivpvX z8OA== X-Gm-Message-State: AMke39n91EPDOkTCbz0eZ4zYKPenCaSe8CIlJ2Q2QsJSb16E2leXxEUL0tnYHTPItJCC7Q== X-Received: by 10.99.114.70 with SMTP id c6mr43891172pgn.163.1489495025807; Tue, 14 Mar 2017 05:37:05 -0700 (PDT) Received: from roar.local0.net ([203.221.48.234]) by smtp.gmail.com with ESMTPSA id s4sm38503847pfi.74.2017.03.14.05.37.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Mar 2017 05:37:04 -0700 (PDT) From: Nicholas Piggin To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 2/6] powerpc/64s: clean up machine check recovery flushing Date: Tue, 14 Mar 2017 22:36:44 +1000 Message-Id: <20170314123648.26068-3-npiggin@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170314123648.26068-1-npiggin@gmail.com> References: <20170314123648.26068-1-npiggin@gmail.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicholas Piggin Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Use the flush function introduced with the POWER9 machine check handler for POWER7 and 8, rather than open coding it multiple times in callers. There is a specific ERAT flush type introduced for POWER9, but the POWER7-8 ERAT errors continue to do SLB flushing (which also flushes ERAT), so as not to introduce functional changes with this cleanup patch. Signed-off-by: Nicholas Piggin --- arch/powerpc/kernel/mce_power.c | 97 ++++++++++------------------------------- 1 file changed, 23 insertions(+), 74 deletions(-) diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c index 763d6f58caa8..0f35a88e3655 100644 --- a/arch/powerpc/kernel/mce_power.c +++ b/arch/powerpc/kernel/mce_power.c @@ -161,81 +161,27 @@ static int mce_handle_flush_derrors(uint64_t dsisr, uint64_t slb, uint64_t tlb, return 1; } -static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits) -{ - long handled = 1; - - /* - * flush and reload SLBs for SLB errors and flush TLBs for TLB errors. - * reset the error bits whenever we handle them so that at the end - * we can check whether we handled all of them or not. - * */ -#ifdef CONFIG_PPC_STD_MMU_64 - if (dsisr & slb_error_bits) { - flush_and_reload_slb(); - /* reset error bits */ - dsisr &= ~(slb_error_bits); - } - if (dsisr & P7_DSISR_MC_TLB_MULTIHIT_MFTLB) { - if (cur_cpu_spec && cur_cpu_spec->flush_tlb) - cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_GLOBAL); - /* reset error bits */ - dsisr &= ~P7_DSISR_MC_TLB_MULTIHIT_MFTLB; - } -#endif - /* Any other errors we don't understand? */ - if (dsisr & 0xffffffffUL) - handled = 0; - - return handled; -} - static long mce_handle_derror_p7(uint64_t dsisr) { - return mce_handle_derror(dsisr, P7_DSISR_MC_SLB_ERRORS); + return mce_handle_flush_derrors(dsisr, + P7_DSISR_MC_SLB_ERRORS, + P7_DSISR_MC_TLB_MULTIHIT_MFTLB, + 0); } -static long mce_handle_common_ierror(uint64_t srr1) +static long mce_handle_ierror_p7(uint64_t srr1) { - long handled = 0; - switch (P7_SRR1_MC_IFETCH(srr1)) { - case 0: - break; -#ifdef CONFIG_PPC_STD_MMU_64 case P7_SRR1_MC_IFETCH_SLB_PARITY: case P7_SRR1_MC_IFETCH_SLB_MULTIHIT: - /* flush and reload SLBs for SLB errors. */ - flush_and_reload_slb(); - handled = 1; - break; + case P7_SRR1_MC_IFETCH_SLB_BOTH: + return mce_flush(MCE_FLUSH_SLB); + case P7_SRR1_MC_IFETCH_TLB_MULTIHIT: - if (cur_cpu_spec && cur_cpu_spec->flush_tlb) { - cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_GLOBAL); - handled = 1; - } - break; -#endif + return mce_flush(MCE_FLUSH_TLB); default: - break; - } - - return handled; -} - -static long mce_handle_ierror_p7(uint64_t srr1) -{ - long handled = 0; - - handled = mce_handle_common_ierror(srr1); - -#ifdef CONFIG_PPC_STD_MMU_64 - if (P7_SRR1_MC_IFETCH(srr1) == P7_SRR1_MC_IFETCH_SLB_BOTH) { - flush_and_reload_slb(); - handled = 1; + return 0; } -#endif - return handled; } static void mce_get_common_ierror(struct mce_error_info *mce_err, uint64_t srr1) @@ -376,22 +322,25 @@ static void mce_get_derror_p8(struct mce_error_info *mce_err, uint64_t dsisr) static long mce_handle_ierror_p8(uint64_t srr1) { - long handled = 0; - - handled = mce_handle_common_ierror(srr1); + switch (P7_SRR1_MC_IFETCH(srr1)) { + case P7_SRR1_MC_IFETCH_SLB_PARITY: + case P7_SRR1_MC_IFETCH_SLB_MULTIHIT: + case P8_SRR1_MC_IFETCH_ERAT_MULTIHIT: + return mce_flush(MCE_FLUSH_SLB); -#ifdef CONFIG_PPC_STD_MMU_64 - if (P7_SRR1_MC_IFETCH(srr1) == P8_SRR1_MC_IFETCH_ERAT_MULTIHIT) { - flush_and_reload_slb(); - handled = 1; + case P7_SRR1_MC_IFETCH_TLB_MULTIHIT: + return mce_flush(MCE_FLUSH_TLB); + default: + return 0; } -#endif - return handled; } static long mce_handle_derror_p8(uint64_t dsisr) { - return mce_handle_derror(dsisr, P8_DSISR_MC_SLB_ERRORS); + return mce_handle_flush_derrors(dsisr, + P8_DSISR_MC_SLB_ERRORS, + P7_DSISR_MC_TLB_MULTIHIT_MFTLB, + 0); } long __machine_check_early_realmode_p8(struct pt_regs *regs)