From patchwork Mon Feb 20 19:44:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 730174 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vRvQ811t6z9s9j for ; Tue, 21 Feb 2017 06:51:12 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="slC/Uk2N"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3vRvQ76sgRzDqD0 for ; Tue, 21 Feb 2017 06:51:11 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="slC/Uk2N"; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from mail-pg0-x243.google.com (mail-pg0-x243.google.com [IPv6:2607:f8b0:400e:c05::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3vRvGz1XdkzDqHK for ; Tue, 21 Feb 2017 06:44:59 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="slC/Uk2N"; dkim-atps=neutral Received: by mail-pg0-x243.google.com with SMTP id 1so6988958pgz.2 for ; Mon, 20 Feb 2017 11:44:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Dw3TBV59+w/fhzdIMrKeh28OcRYwvKEnoEFGQCkyvw0=; b=slC/Uk2NXgQQQ8hziRQFVBn4ltEOjn+pFqt1XvJaFe9stk7f7ODRq7rKNlGdiumcHy dCNaFdyAlnvQnO89gk7aq4MUZI8ExkksVxrJ1EG7OXDNEJPOp/Y8YHa5yb32lzDsywVl TyvNAfL21RsXHvqQQKtYXXKRyRgMpfshylQM2H4Q0kCksIIbBQFTVrdKOxHSJWeJLdxH ePR5x5CaLUXdXZ9+4mu187OWAMp0mYZlw6SwlAbee94wdCQEfCSP2Xa91xOjSQEZKqnM n4RD6b2EpXiDf5Eh/prUSH6XY8CG51P/+1efVO49vb1KkcPYakpGsa8TaZaZ9SK2IjPk TkJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Dw3TBV59+w/fhzdIMrKeh28OcRYwvKEnoEFGQCkyvw0=; b=BeICO8SQnoI4BsL0J6lGylo5StrDuOVlY1QdZC3TlxM5OEDMTlPB1ELkahSP5tNNLB B2qzeqLcnN8lg46+amoprQkNlM1Kmzu21sIu3008o9m8JShHfPoiLRpCzS8MJuf2OrWr EzZiMTf2t06m0nxzAFp1YK8CtfqWTvc1sc9ZFPZ2YIw7o2AOAmrOEKZFNIYsBVu2nNfp YKUvriaH1l8+JYpJ6h4Vx3ehDJ2euF7HvVdX3fXD3ajjDuQGDdihFIt/LfwY4qXIA1e/ 5y5ylC80kvjEziYN3TezSE9ss37MufZ+X+PmF/+MwjV2D+bUJdQN4/+eaFDaysSLoJPj t1hQ== X-Gm-Message-State: AMke39nFXlFfcYQA/di1kU9gpov3w15KlBX+GwJD3Z3B1sc4SBTs0TVWMD74/ttfxI9ZfQ== X-Received: by 10.99.127.89 with SMTP id p25mr9855758pgn.101.1487619897584; Mon, 20 Feb 2017 11:44:57 -0800 (PST) Received: from roar.au.ibm.com ([203.221.48.234]) by smtp.gmail.com with ESMTPSA id i10sm36813303pgd.37.2017.02.20.11.44.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 20 Feb 2017 11:44:56 -0800 (PST) From: Nicholas Piggin To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 3/9] powerpc/64s: clean up machine check recovery flushing Date: Tue, 21 Feb 2017 05:44:24 +1000 Message-Id: <20170220194430.32602-4-npiggin@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170220194430.32602-1-npiggin@gmail.com> References: <20170220194430.32602-1-npiggin@gmail.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicholas Piggin , Mahesh Salgaonkar Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Put the ifdefs into a flush handler call, and have callers ask for particular type of flushes. Also add an ERAT flush type (although existing ERAT flushing goes to the SLB flush path). Signed-off-by: Nicholas Piggin --- arch/powerpc/kernel/mce_power.c | 124 +++++++++++++++++++--------------------- 1 file changed, 59 insertions(+), 65 deletions(-) diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c index c37fc5fdd433..07af815b5ba1 100644 --- a/arch/powerpc/kernel/mce_power.c +++ b/arch/powerpc/kernel/mce_power.c @@ -114,83 +114,74 @@ static void flush_and_reload_slb(void) asm volatile("slbmte %0,%1" : : "r" (rs), "r" (rb)); } } -#endif -static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits) +static void flush_erat(void) { - long handled = 1; + asm volatile(PPC_INVALIDATE_ERAT : : :"memory"); +} +#endif - /* - * flush and reload SLBs for SLB errors and flush TLBs for TLB errors. - * reset the error bits whenever we handle them so that at the end - * we can check whether we handled all of them or not. - * */ +#define MCE_FLUSH_SLB 1 +#define MCE_FLUSH_TLB 2 +#define MCE_FLUSH_ERAT 3 + +static int mce_flush(int what) +{ #ifdef CONFIG_PPC_STD_MMU_64 - if (dsisr & slb_error_bits) { + if (what == MCE_FLUSH_SLB) { flush_and_reload_slb(); - /* reset error bits */ - dsisr &= ~(slb_error_bits); + return 1; } - if (dsisr & P7_DSISR_MC_TLB_MULTIHIT_MFTLB) { - if (cur_cpu_spec && cur_cpu_spec->flush_tlb) - cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_GLOBAL); - /* reset error bits */ - dsisr &= ~P7_DSISR_MC_TLB_MULTIHIT_MFTLB; + if (what == MCE_FLUSH_ERAT) { + flush_erat(); + return 1; } #endif - /* Any other errors we don't understand? */ - if (dsisr & 0xffffffffUL) - handled = 0; + if (what == MCE_FLUSH_TLB) { + if (cur_cpu_spec && cur_cpu_spec->flush_tlb) { + cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_GLOBAL); + return 1; + } + } - return handled; + return 0; } -static long mce_handle_derror_p7(uint64_t dsisr) +static int mce_handle_flush_derrors(uint64_t dsisr, uint64_t slb, uint64_t tlb, uint64_t erat) { - return mce_handle_derror(dsisr, P7_DSISR_MC_SLB_ERRORS); + if ((dsisr & slb) && mce_flush(MCE_FLUSH_SLB)) + dsisr &= ~slb; + if ((dsisr & erat) && mce_flush(MCE_FLUSH_ERAT)) + dsisr &= ~erat; + if ((dsisr & tlb) && mce_flush(MCE_FLUSH_TLB)) + dsisr &= ~tlb; + /* Any other errors we don't understand? */ + if (dsisr) + return 0; + return 1; } -static long mce_handle_common_ierror(uint64_t srr1) +static long mce_handle_derror_p7(uint64_t dsisr) { - long handled = 0; + return mce_handle_flush_derrors(dsisr, + P7_DSISR_MC_SLB_ERRORS, + P7_DSISR_MC_TLB_MULTIHIT_MFTLB, + 0); +} +static long mce_handle_ierror_p7(uint64_t srr1) +{ switch (P7_SRR1_MC_IFETCH(srr1)) { - case 0: - break; -#ifdef CONFIG_PPC_STD_MMU_64 case P7_SRR1_MC_IFETCH_SLB_PARITY: case P7_SRR1_MC_IFETCH_SLB_MULTIHIT: - /* flush and reload SLBs for SLB errors. */ - flush_and_reload_slb(); - handled = 1; - break; + case P7_SRR1_MC_IFETCH_SLB_BOTH: + return mce_flush(MCE_FLUSH_SLB); + case P7_SRR1_MC_IFETCH_TLB_MULTIHIT: - if (cur_cpu_spec && cur_cpu_spec->flush_tlb) { - cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_GLOBAL); - handled = 1; - } - break; -#endif + return mce_flush(MCE_FLUSH_TLB); default: - break; - } - - return handled; -} - -static long mce_handle_ierror_p7(uint64_t srr1) -{ - long handled = 0; - - handled = mce_handle_common_ierror(srr1); - -#ifdef CONFIG_PPC_STD_MMU_64 - if (P7_SRR1_MC_IFETCH(srr1) == P7_SRR1_MC_IFETCH_SLB_BOTH) { - flush_and_reload_slb(); - handled = 1; + return 0; } -#endif - return handled; } static void mce_get_common_ierror(struct mce_error_info *mce_err, uint64_t srr1) @@ -331,22 +322,25 @@ static void mce_get_derror_p8(struct mce_error_info *mce_err, uint64_t dsisr) static long mce_handle_ierror_p8(uint64_t srr1) { - long handled = 0; - - handled = mce_handle_common_ierror(srr1); + switch (P7_SRR1_MC_IFETCH(srr1)) { + case P7_SRR1_MC_IFETCH_SLB_PARITY: + case P7_SRR1_MC_IFETCH_SLB_MULTIHIT: + case P8_SRR1_MC_IFETCH_ERAT_MULTIHIT: + return mce_flush(MCE_FLUSH_SLB); -#ifdef CONFIG_PPC_STD_MMU_64 - if (P7_SRR1_MC_IFETCH(srr1) == P8_SRR1_MC_IFETCH_ERAT_MULTIHIT) { - flush_and_reload_slb(); - handled = 1; + case P7_SRR1_MC_IFETCH_TLB_MULTIHIT: + return mce_flush(MCE_FLUSH_TLB); + default: + return 0; } -#endif - return handled; } static long mce_handle_derror_p8(uint64_t dsisr) { - return mce_handle_derror(dsisr, P8_DSISR_MC_SLB_ERRORS); + return mce_handle_flush_derrors(dsisr, + P8_DSISR_MC_SLB_ERRORS, + P7_DSISR_MC_TLB_MULTIHIT_MFTLB, + 0); } long __machine_check_early_realmode_p8(struct pt_regs *regs)