From patchwork Thu Sep 22 04:35:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 673125 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3sfkGf00qrz9sC3 for ; Thu, 22 Sep 2016 14:36:42 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=fQfOR81t; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3sfkGd67tRzDsk2 for ; Thu, 22 Sep 2016 14:36:41 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=fQfOR81t; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from mail-pf0-x243.google.com (mail-pf0-x243.google.com [IPv6:2607:f8b0:400e:c00::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3sfkDz0SYjzDsgg for ; Thu, 22 Sep 2016 14:35:15 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=fQfOR81t; dkim-atps=neutral Received: by mail-pf0-x243.google.com with SMTP id 6so3225961pfl.2 for ; Wed, 21 Sep 2016 21:35:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=date:from:to:cc:subject:message-id:in-reply-to:references :organization:mime-version:content-transfer-encoding; bh=tJDQOkHY+9OcfAcOOY9QEUrZ+tF2WVl5l45EpRYKImo=; b=fQfOR81tpCfCSF47U+8HeSCO4cLSjJJmscGYLSOatuuRJZkSXB56NUj/mXefkDXNsP HXUEhr4ZLWPq5u33N2yzVOrLjLNPHSuwyS1NV2FZhAJara0rX2zNao+2uPVkNdMaL/ac uHfJ3syrQMrASohiFpRlQKf8qfnob+cHBSXW45btDNsagOTsLQR5/Taiamo1QVKJTHCQ Q6cGF05uViP90PCceMyPp+jUBZsltpqIy/6IVphYh3O1YcvoUCWlSYgkPogUXCGlRzup +Oss/ywA7kSeLP7i3hb399dbebgxQ9yo02tIwwgHUfe3soX0I/JLdZ7zUmu6W4YzIEYP ROJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:in-reply-to :references:organization:mime-version:content-transfer-encoding; bh=tJDQOkHY+9OcfAcOOY9QEUrZ+tF2WVl5l45EpRYKImo=; b=NBjzSOp8rJD1IP7zcWU+ne6GWAO4bH0ismZvNPxulJfdyHKYRskfpM7nUL45FfvWwP ssedv5BOMNPWkxWQZ2omqKD0es9IJK7e8ezxRTlgcN4eyoLdoP39y67nN7uiAx4xgION buKzIRuTXWX04kQXmQ9pQMDNRmUMjd/LSgiPzFF57tx2fp2XOf0ZTBBxwzy6DXuFTnD0 WbCETNnLgKQRP1g8hS03ozlRt1+95X45ItW/wBQRWWh5RKUnzJEy0hB9rQGbx2d+KYj8 FCvBwPWxvA70PBXO64w3pzSdLHMq8gAAR9r8Ve6fh/Wag4RbnNtt3B61OujQIEVUvq4W 4mmA== X-Gm-Message-State: AE9vXwO7GP10i5Xktj6n2ZHjc4nqrBJ+cWiJE3by4LNQX/UxonKm7EeiNu2EaG3DfH/nZA== X-Received: by 10.98.106.65 with SMTP id f62mr72301253pfc.107.1474518913055; Wed, 21 Sep 2016 21:35:13 -0700 (PDT) Received: from roar.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id b64sm1254919pfa.82.2016.09.21.21.35.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 21 Sep 2016 21:35:12 -0700 (PDT) Date: Thu, 22 Sep 2016 14:35:00 +1000 From: Nicholas Piggin To: Tejun Heo Subject: Re: [PATCH] percpu: improve generic percpu modify-return implementation Message-ID: <20160922143500.21809b98@roar.ozlabs.ibm.com> In-Reply-To: <20160921142343.GA10734@htj.duckdns.org> References: <20160921085137.862-1-npiggin@gmail.com> <20160921205711.4e804777@roar.ozlabs.ibm.com> <20160921142343.GA10734@htj.duckdns.org> Organization: IBM X-Mailer: Claws Mail 3.14.0 (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, Christoph Lameter , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Wed, 21 Sep 2016 10:23:43 -0400 Tejun Heo wrote: > Hello, Nick. > > How have you been? :) Hey Tejun, Well thank you, how about you? > On Wed, Sep 21, 2016 at 08:57:11PM +1000, Nicholas Piggin wrote: > > On Wed, 21 Sep 2016 18:51:37 +1000 > > Nicholas Piggin wrote: > > > > > Some architectures require an additional load to find the address of > > > percpu pointers. In some implemenatations, the C aliasing rules do not > > > allow the result of that load to be kept over the store that modifies > > > the percpu variable, which causes additional loads. > > > > Sorry I picked up an old patch here. This one should be better. > > > > From d0cb9052d6f4c31d24f999b7b0cecb34681eee9b Mon Sep 17 00:00:00 2001 > > From: Nicholas Piggin > > Date: Wed, 21 Sep 2016 18:23:43 +1000 > > Subject: [PATCH] percpu: improve generic percpu modify-return implementations > > > > Some architectures require an additional load to find the address of > > percpu pointers. In some implemenatations, the C aliasing rules do not > > allow the result of that load to be kept over the store that modifies > > the percpu variable, which causes additional loads. > > > > Work around this by finding the pointer first, then operating on that. > > > > It's also possible to mark things as restrict and those kind of games, > > but that can require larger and arch specific changes. > > > > On powerpc, __this_cpu_inc_return compiles to: > > > > ld 10,48(13) > > ldx 9,3,10 > > addi 9,9,1 > > stdx 9,3,10 > > ld 9,48(13) > > ldx 3,9,3 > > > > With this patch it compiles to: > > > > ld 10,48(13) > > ldx 9,3,10 > > addi 9,9,1 > > stdx 9,3,10 > > > > Signed-off-by: Nicholas Piggin > > Patch looks good to me but seems QP encoded. Can you please resend? > > Thanks and it's great to see you again! > Trying a new mail client, sorry. It *seems* to be working now, how's this? From d0cb9052d6f4c31d24f999b7b0cecb34681eee9b Mon Sep 17 00:00:00 2001 From: Nicholas Piggin Date: Wed, 21 Sep 2016 18:23:43 +1000 Subject: [PATCH] percpu: improve generic percpu modify-return implementations Some architectures require an additional load to find the address of percpu pointers. In some implemenatations, the C aliasing rules do not allow the result of that load to be kept over the store that modifies the percpu variable, which causes additional loads. Work around this by finding the pointer first, then operating on that. It's also possible to mark things as restrict and those kind of games, but that can require larger and arch specific changes. On powerpc, __this_cpu_inc_return compiles to: ld 10,48(13) ldx 9,3,10 addi 9,9,1 stdx 9,3,10 ld 9,48(13) ldx 3,9,3 With this patch it compiles to: ld 10,48(13) ldx 9,3,10 addi 9,9,1 stdx 9,3,10 Signed-off-by: Nicholas Piggin To: Tejun Heo To: Christoph Lameter Cc: linux-kernel@vger.kernel.org Cc: linux-arch@vger.kernel.org --- include/asm-generic/percpu.h | 53 +++++++++++++++++++++++++------------------- 1 file changed, 30 insertions(+), 23 deletions(-) diff --git a/include/asm-generic/percpu.h b/include/asm-generic/percpu.h index 4d9f233..40e8870 100644 --- a/include/asm-generic/percpu.h +++ b/include/asm-generic/percpu.h @@ -65,6 +65,11 @@ extern void setup_per_cpu_areas(void); #define PER_CPU_DEF_ATTRIBUTES #endif +#define raw_cpu_generic_read(pcp) \ +({ \ + *raw_cpu_ptr(&(pcp)); \ +}) + #define raw_cpu_generic_to_op(pcp, val, op) \ do { \ *raw_cpu_ptr(&(pcp)) op val; \ @@ -72,34 +77,39 @@ do { \ #define raw_cpu_generic_add_return(pcp, val) \ ({ \ - raw_cpu_add(pcp, val); \ - raw_cpu_read(pcp); \ + typeof(&(pcp)) __p = raw_cpu_ptr(&(pcp)); \ + \ + *__p += val; \ + *__p; \ }) #define raw_cpu_generic_xchg(pcp, nval) \ ({ \ + typeof(&(pcp)) __p = raw_cpu_ptr(&(pcp)); \ typeof(pcp) __ret; \ - __ret = raw_cpu_read(pcp); \ - raw_cpu_write(pcp, nval); \ + __ret = *__p; \ + *__p = nval; \ __ret; \ }) #define raw_cpu_generic_cmpxchg(pcp, oval, nval) \ ({ \ + typeof(&(pcp)) __p = raw_cpu_ptr(&(pcp)); \ typeof(pcp) __ret; \ - __ret = raw_cpu_read(pcp); \ + __ret = *__p; \ if (__ret == (oval)) \ - raw_cpu_write(pcp, nval); \ + *__p = nval; \ __ret; \ }) #define raw_cpu_generic_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2) \ ({ \ + typeof(&(pcp1)) __p1 = raw_cpu_ptr(&(pcp1)); \ + typeof(&(pcp2)) __p2 = raw_cpu_ptr(&(pcp2)); \ int __ret = 0; \ - if (raw_cpu_read(pcp1) == (oval1) && \ - raw_cpu_read(pcp2) == (oval2)) { \ - raw_cpu_write(pcp1, nval1); \ - raw_cpu_write(pcp2, nval2); \ + if (*__p1 == (oval1) && *__p2 == (oval2)) { \ + *__p1 = nval1; \ + *__p2 = nval2; \ __ret = 1; \ } \ (__ret); \ @@ -109,7 +119,7 @@ do { \ ({ \ typeof(pcp) __ret; \ preempt_disable(); \ - __ret = *this_cpu_ptr(&(pcp)); \ + __ret = raw_cpu_generic_read(pcp); \ preempt_enable(); \ __ret; \ }) @@ -118,17 +128,17 @@ do { \ do { \ unsigned long __flags; \ raw_local_irq_save(__flags); \ - *raw_cpu_ptr(&(pcp)) op val; \ + raw_cpu_generic_to_op(pcp, val, op); \ raw_local_irq_restore(__flags); \ } while (0) + #define this_cpu_generic_add_return(pcp, val) \ ({ \ typeof(pcp) __ret; \ unsigned long __flags; \ raw_local_irq_save(__flags); \ - raw_cpu_add(pcp, val); \ - __ret = raw_cpu_read(pcp); \ + __ret = raw_cpu_generic_add_return(pcp, val); \ raw_local_irq_restore(__flags); \ __ret; \ }) @@ -138,8 +148,7 @@ do { \ typeof(pcp) __ret; \ unsigned long __flags; \ raw_local_irq_save(__flags); \ - __ret = raw_cpu_read(pcp); \ - raw_cpu_write(pcp, nval); \ + __ret = raw_cpu_generic_xchg(pcp, nval); \ raw_local_irq_restore(__flags); \ __ret; \ }) @@ -149,9 +158,7 @@ do { \ typeof(pcp) __ret; \ unsigned long __flags; \ raw_local_irq_save(__flags); \ - __ret = raw_cpu_read(pcp); \ - if (__ret == (oval)) \ - raw_cpu_write(pcp, nval); \ + __ret = raw_cpu_generic_cmpxchg(pcp, oval, nval); \ raw_local_irq_restore(__flags); \ __ret; \ }) @@ -168,16 +175,16 @@ do { \ }) #ifndef raw_cpu_read_1 -#define raw_cpu_read_1(pcp) (*raw_cpu_ptr(&(pcp))) +#define raw_cpu_read_1(pcp) raw_cpu_generic_read(pcp) #endif #ifndef raw_cpu_read_2 -#define raw_cpu_read_2(pcp) (*raw_cpu_ptr(&(pcp))) +#define raw_cpu_read_2(pcp) raw_cpu_generic_read(pcp) #endif #ifndef raw_cpu_read_4 -#define raw_cpu_read_4(pcp) (*raw_cpu_ptr(&(pcp))) +#define raw_cpu_read_4(pcp) raw_cpu_generic_read(pcp) #endif #ifndef raw_cpu_read_8 -#define raw_cpu_read_8(pcp) (*raw_cpu_ptr(&(pcp))) +#define raw_cpu_read_8(pcp) raw_cpu_generic_read(pcp) #endif #ifndef raw_cpu_write_1