From patchwork Fri Jun 10 03:51:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Boqun Feng X-Patchwork-Id: 633491 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rQp8B0NLJz9sBM for ; Fri, 10 Jun 2016 13:49:30 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=sH8sh2H9; dkim-atps=neutral Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3rQp8962KXzDqW8 for ; Fri, 10 Jun 2016 13:49:29 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=sH8sh2H9; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from mail-it0-x243.google.com (mail-it0-x243.google.com [IPv6:2607:f8b0:4001:c0b::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3rQp6Y4B10zDq5s for ; Fri, 10 Jun 2016 13:48:05 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=sH8sh2H9; dkim-atps=neutral Received: by mail-it0-x243.google.com with SMTP id i6so794478ith.0 for ; Thu, 09 Jun 2016 20:48:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=aGmdgqxFlI+clUb0oNrRtQ/4dv4hwmPyfrwWeRKe8fs=; b=sH8sh2H9bPsXKRJQDKFfWK3NAmGHr9AI2HgJLPnBj7SYr/GjvtvLM3ayJu8yRS440F JNszsD6ztoYqFRQLJjDw94S4wG6g56HaCjPVm7K58Ce43eHBJeGLBCXn0g+Tjww37RFS 5TY3BXbRrRP7LcrPQwuc9fdGEwDq0UAy1qRx8nzbTbnJp8GY/tlFvoc2osRNmZ7gwJTq fVLayZueVaffo2jua4Zgxda/Q5sHNHbRVoa3vWAqPa/G4Otyc4BHL1XFFpiUqrz2i/mb HefH7gwMAoUxWvXKriBbNJ6R8APofVi74dp+bJmuIH7QBFOsK+tzNoXDIhYfU5SFw8aU 4QKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=aGmdgqxFlI+clUb0oNrRtQ/4dv4hwmPyfrwWeRKe8fs=; b=jafQ4Fuud5n00YC97ZIxJwmTwOYgwNq3kLqabtNyhB8qD5wC9+PIvc+CcwjYzPLMok PTVRBQIYrXOCQVMnetwt2lRfhEt7UMPiNdu6IzdMPT4/2rmghBqJezZMaMP0sQ7AYz+k mP8z+z6xPbZ1VXj3MBFde1ZaEkX0aZ4fVEtNu2Lzy31NPEZ+T4iwiDfClGFD9QhRbCe7 zI+w+Ki5PFzOElRZLfsQSdQkZE2rJtmepCTNxbQfyluaOIlZjJZykbgG0mp/uQys0RqO 8skbnz0GYaQ6tSCVncK/U+Qafth+0KBqFbz1bqYdsSYdWXoB8nnzhfq+xNyCKOmFxM1a fbww== X-Gm-Message-State: ALyK8tIfAnnIBAUkqfUu4MKUmqvxC6uk4q78as0eHVaONQ9c7qV+oOeYjDahGtmWyN9pjw== X-Received: by 10.36.51.15 with SMTP id k15mr26141034itk.80.1465530483652; Thu, 09 Jun 2016 20:48:03 -0700 (PDT) Received: from localhost ([106.38.0.83]) by smtp.gmail.com with ESMTPSA id k15sm4716453iod.22.2016.06.09.20.48.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Jun 2016 20:48:02 -0700 (PDT) From: Boqun Feng To: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Subject: [PATCH v4] powerpc: spinlock: Fix spin_unlock_wait() Date: Fri, 10 Jun 2016 11:51:28 +0800 Message-Id: <20160610035128.21087-1-boqun.feng@gmail.com> X-Mailer: git-send-email 2.8.3 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Zijlstra , Boqun Feng , Will Deacon , Alexander Graf , Paul Mackerras , "Suresh E. Warrier" , "Paul E. McKenney" MIME-Version: 1.0 Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" There is an ordering issue with spin_unlock_wait() on powerpc, because the spin_lock primitive is an ACQUIRE and an ACQUIRE is only ordering the load part of the operation with memory operations following it. Therefore the following event sequence can happen: CPU 1 CPU 2 CPU 3 ================== ==================== ============== spin_unlock(&lock); spin_lock(&lock): r1 = *lock; // r1 == 0; o = object; o = READ_ONCE(object); // reordered here object = NULL; smp_mb(); spin_unlock_wait(&lock); *lock = 1; smp_mb(); o->dead = true; < o = READ_ONCE(object); > // reordered upwards if (o) // true BUG_ON(o->dead); // true!! To fix this, we add a "nop" ll/sc loop in arch_spin_unlock_wait() on ppc, the "nop" ll/sc loop reads the lock value and writes it back atomically, in this way it will synchronize the view of the lock on CPU1 with that on CPU2. Therefore in the scenario above, either CPU2 will fail to get the lock at first or CPU1 will see the lock acquired by CPU2, both cases will eliminate this bug. This is a similar idea as what Will Deacon did for ARM64 in: d86b8da04dfa ("arm64: spinlock: serialise spin_unlock_wait against concurrent lockers") Furthermore, if the "nop" ll/sc figures out the lock is locked, we actually don't need to do the "nop" ll/sc trick again, we can just do a normal load+check loop for the lock to be released, because in that case, spin_unlock_wait() is called when someone is holding the lock, and the store part of the "nop" ll/sc happens before the lock release of the current lock holder: "nop" ll/sc -> spin_unlock() and the lock release happens before the next lock acquisition: spin_unlock() -> spin_lock() which means the "nop" ll/sc happens before the next lock acquisition: "nop" ll/sc -> spin_unlock() -> spin_lock() With a smp_mb() preceding spin_unlock_wait(), the store of object is guaranteed to be observed by the next lock holder: STORE -> smp_mb() -> "nop" ll/sc -> spin_unlock() -> spin_lock() This patch therefore fixes the issue and also cleans the arch_spin_unlock_wait() a little bit by removing superfluous memory barriers in loops and consolidating the implementations for PPC32 and PPC64 into one. Suggested-by: "Paul E. McKenney" Signed-off-by: Boqun Feng Reviewed-by: "Paul E. McKenney" [mpe: Inline the "nop" ll/sc loop and set EH=0, munge change log] Signed-off-by: Michael Ellerman --- v4 (boqun): - replace !arch_spin_value_unlocked() with lock->slock in the loop condition to avoid a bug caused by compiler optimization. v3 (mpe): - Inline the ll/sc loop. - Change the EH on the LWARX to 0 - Rewrite change log to cope with the fact we removed arch_spin_is_locked_sync() v1-->v2: - Improve the commit log, suggested by Peter Zijlstra - Keep two smp_mb()s for the safety, which though could be deleted if all the users have been aduited and fixed later. arch/powerpc/include/asm/spinlock.h | 38 +++++++++++++++++++++++++++++++------ arch/powerpc/lib/locks.c | 16 ---------------- 2 files changed, 32 insertions(+), 22 deletions(-) diff --git a/arch/powerpc/include/asm/spinlock.h b/arch/powerpc/include/asm/spinlock.h index 523673d7583c..fa37fe93bc02 100644 --- a/arch/powerpc/include/asm/spinlock.h +++ b/arch/powerpc/include/asm/spinlock.h @@ -162,12 +162,38 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock) lock->slock = 0; } -#ifdef CONFIG_PPC64 -extern void arch_spin_unlock_wait(arch_spinlock_t *lock); -#else -#define arch_spin_unlock_wait(lock) \ - do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0) -#endif +static inline void arch_spin_unlock_wait(arch_spinlock_t *lock) +{ + arch_spinlock_t lock_val; + + smp_mb(); + + /* + * Atomically load and store back the lock value (unchanged). This + * ensures that our observation of the lock value is ordered with + * respect to other lock operations. + */ + __asm__ __volatile__( +"1: " PPC_LWARX(%0, 0, %2, 0) "\n" +" stwcx. %0, 0, %2\n" +" bne- 1b\n" + : "=&r" (lock_val), "+m" (*lock) + : "r" (lock) + : "cr0", "xer"); + + if (arch_spin_value_unlocked(lock_val)) + goto out; + + while (lock->slock) { + HMT_low(); + if (SHARED_PROCESSOR) + __spin_yield(lock); + } + HMT_medium(); + +out: + smp_mb(); +} /* * Read-write spinlocks, allowing multiple readers diff --git a/arch/powerpc/lib/locks.c b/arch/powerpc/lib/locks.c index f7deebdf3365..b7b1237d4aa6 100644 --- a/arch/powerpc/lib/locks.c +++ b/arch/powerpc/lib/locks.c @@ -68,19 +68,3 @@ void __rw_yield(arch_rwlock_t *rw) get_hard_smp_processor_id(holder_cpu), yield_count); } #endif - -void arch_spin_unlock_wait(arch_spinlock_t *lock) -{ - smp_mb(); - - while (lock->slock) { - HMT_low(); - if (SHARED_PROCESSOR) - __spin_yield(lock); - } - HMT_medium(); - - smp_mb(); -} - -EXPORT_SYMBOL(arch_spin_unlock_wait);