From patchwork Fri Sep 25 01:35:28 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rex Feany X-Patchwork-Id: 34244 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from bilbo.ozlabs.org (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id CFC1EB7C08 for ; Fri, 25 Sep 2009 11:35:40 +1000 (EST) Received: by ozlabs.org (Postfix) id B4762B7B81; Fri, 25 Sep 2009 11:35:33 +1000 (EST) Delivered-To: linuxppc-dev@ozlabs.org Received: from bos-spam.mrv.com (mx5.mrv.com [140.179.254.12]) by ozlabs.org (Postfix) with ESMTP id 3D6C4B7B80 for ; Fri, 25 Sep 2009 11:35:33 +1000 (EST) X-ASG-Debug-ID: 1253842530-61a300020001-myxymE Received: from bosmail.bos.mrv.com (bosmail.bos.mrv.com [140.179.176.26]) by bos-spam.mrv.com with ESMTP id FuLs9HI4j9goXuCJ; Thu, 24 Sep 2009 21:35:30 -0400 (EDT) X-Barracuda-Envelope-From: RFeany@mrv.com Received: from chmailsrv.int.mrv.com ([192.168.11.19]) by bosmail.bos.mrv.com with Microsoft SMTPSVC(6.0.3790.1830); Thu, 24 Sep 2009 21:36:22 -0400 Received: from jane.chatsunix.int.mrv.com ([192.168.11.80]) by chmailsrv.int.mrv.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 24 Sep 2009 18:36:20 -0700 X-Barracuda-BBL-IP: 192.168.11.19 X-Barracuda-RBL-IP: 192.168.11.19 Received: from compile2.chatsunix.int.mrv.com ([192.168.17.15]) by jane.chatsunix.int.mrv.com with esmtp (Exim 4.69) (envelope-from ) id 1Mqzia-0004vw-Vc; Thu, 24 Sep 2009 18:35:29 -0700 Received: from rfeany by compile2.chatsunix.int.mrv.com with local (Exim 4.69) (envelope-from ) id 1Mqzia-0003SW-SI; Thu, 24 Sep 2009 18:35:28 -0700 Date: Thu, 24 Sep 2009 18:35:28 -0700 From: Rex Feany To: Benjamin Herrenschmidt X-ASG-Orig-Subj: Re: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite Subject: Re: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite Message-ID: <20090925013528.GA2584@compile2.chatsunix.int.mrv.com> References: <20090924004552.GA11737@compile2.chatsunix.int.mrv.com> <1253774659.7103.405.camel@pasglop> <20090924233346.GA445@compile2.chatsunix.int.mrv.com> <1253836376.7103.469.camel@pasglop> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1253836376.7103.469.camel@pasglop> User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 25 Sep 2009 01:36:20.0893 (UTC) FILETIME=[95A0C4D0:01CA3D80] X-Barracuda-Connect: bosmail.bos.mrv.com[140.179.176.26] X-Barracuda-Start-Time: 1253842530 X-Barracuda-URL: http://140.179.128.126:8000/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at mrv.com Cc: "linuxppc-dev@ozlabs.org" X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Thus spake Benjamin Herrenschmidt (benh@kernel.crashing.org): > > Your tree hangs on boot, similar to what I saw without the 8xx > > work-around patch -- it is hard to tell if it is the same though. :( > > There's no backtrace ? Where does it hang ? Also which workaround > patch ? The missing tlbil_va() or the _PAGE_SPECIAL problem ? > Ben, I'm sorry, my last email was basically useless. I was refering to the missing tlbil_va(). The system doesn't crash, but it does seem to hang right after "Freeing unused kernel memory: 100k init" using your tree. If I move the tlbil_va() outside of the test for PG_arch_1 : Then I can boot and get to a shell, but userspace is slow. 8 seconds to mount /proc (vs. less then a second using my old kernel)! Maybe this is an unrelated issue? I'm pretty clueless about the details, I'm sorry. PG_arch_1 is used to prevent a cache flush unless it is actually needed? Then why would changing the location of the tlbil_va() make a difference? take care! /rex. diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c index 5304093..d927269 100644 --- a/arch/powerpc/mm/pgtable.c +++ b/arch/powerpc/mm/pgtable.c @@ -176,7 +176,7 @@ static pte_t set_pte_filter(pte_t pte, unsigned long addr) struct page *pg = maybe_pte_to_page(pte); if (!pg) return pte; - if (!test_bit(PG_arch_1, &pg->flags)) { + #ifdef CONFIG_8xx /* On 8xx, cache control instructions (particularly * "dcbst" from flush_dcache_icache) fault as write @@ -188,6 +188,8 @@ static pte_t set_pte_filter(pte_t pte, unsigned long addr) /* 8xx doesn't care about PID, size or ind args */ _tlbil_va(addr, 0, 0, 0); #endif /* CONFIG_8xx */ + + if (!test_bit(PG_arch_1, &pg->flags)) { flush_dcache_icache_page(pg); set_bit(PG_arch_1, &pg->flags); }