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Tue, 05 Oct 2021 10:21:32 -0700 (PDT) Received: from localhost.localdomain ([2406:7400:63:f69:1127:b4ce:ef67:b718]) by smtp.gmail.com with ESMTPSA id f25sm18476722pge.7.2021.10.05.10.21.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Oct 2021 10:21:32 -0700 (PDT) From: Naveen Naidu To: bhelgaas@google.com, ruscur@russell.cc, oohall@gmail.com Subject: [PATCH v4 8/8] PCI/AER: Include DEVCTL in aer_print_error() Date: Tue, 5 Oct 2021 22:48:16 +0530 Message-Id: <18cad894ac3210af806104b3b4fa6a8cf1554ac8.1633453452.git.naveennaidu479@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Naveen Naidu , skhan@linuxfoundation.org, linuxppc-dev@lists.ozlabs.org, linux-kernel-mentees@lists.linuxfoundation.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Print the contents of Device Control Register of the device which detected the error. This might help in faster error diagnosis. Sample output from dummy error injected by aer-inject: pcieport 0000:00:03.0: AER: Corrected error received: 0000:00:03.0 pcieport 0000:00:03.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Receiver) pcieport 0000:00:03.0: device [1b36:000c] error status/mask=00000040/0000e000, devctl=0x000f <-- devctl added to the error log pcieport 0000:00:03.0: [ 6] BadTLP Signed-off-by: Naveen Naidu --- drivers/pci/pci.h | 2 ++ drivers/pci/pcie/aer.c | 10 ++++++++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index eb88d8bfeaf7..48ed7f91113b 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -437,6 +437,8 @@ struct aer_err_info { u32 status; /* COR/UNCOR Error Status */ u32 mask; /* COR/UNCOR Error Mask */ struct aer_header_log_regs tlp; /* TLP Header */ + + u16 devctl; }; /* Preliminary AER error information processed from Root port */ diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index d3937f5384e4..fdeef9deb016 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -729,8 +729,8 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) aer_error_severity_string[info->severity], aer_error_layer[layer], aer_agent_string[agent]); - pci_printk(level, dev, " device [%04x:%04x] error status/mask=%08x/%08x\n", - dev->vendor, dev->device, info->status, info->mask); + pci_printk(level, dev, " device [%04x:%04x] error status/mask=%08x/%08x, devctl=%#06x\n", + dev->vendor, dev->device, info->status, info->mask, info->devctl); __aer_print_error(dev, info); @@ -1083,6 +1083,12 @@ int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info) if (!aer) return 0; + /* + * Cache the value of Device Control Register now, because later the + * device might not be available + */ + pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &info->devctl); + if (info->severity == AER_CORRECTABLE) { pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &info->status);