| Message ID | 1605069189-2740-3-git-send-email-atrajeev@linux.vnet.ibm.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | powerpc/perf: Fixes for power10 PMU | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch powerpc/merge (80ecbe16c827714ce3741ed1f1d34488b903e717) |
| snowpatch_ozlabs/checkpatch | warning | total: 0 errors, 1 warnings, 0 checks, 36 lines checked |
| snowpatch_ozlabs/needsstable | warning | Please consider tagging this patch for stable! |
Athira Rajeev <atrajeev@linux.vnet.ibm.com> writes: > In Power9, L2/L3 bus events are always available as a > "bank" of 4 events. To obtain the counts for any of the > l2/l3 bus events in a given bank, the user will have to > program PMC4 with corresponding l2/l3 bus event for that > bank. > > Commit 59029136d750 ("powerpc/perf: Add constraints for power9 l2/l3 bus events") > enforced this rule in Power9. But this is not valid for > Power10, since in Power10 Monitor Mode Control Register2 > (MMCR2) has bits to configure l2/l3 event bits. Hence remove > this PMC4 constraint check from power10. > > Since the l2/l3 bits in MMCR2 are not per-pmc, patch handles > group constrints checks for l2/l3 bits in MMCR2. > Patch also updates constraints for threshold events in power10. That should be done in a separate patch please. cheers
> On 18-Nov-2020, at 10:02 AM, Michael Ellerman <mpe@ellerman.id.au> wrote: > > Athira Rajeev <atrajeev@linux.vnet.ibm.com> writes: >> In Power9, L2/L3 bus events are always available as a >> "bank" of 4 events. To obtain the counts for any of the >> l2/l3 bus events in a given bank, the user will have to >> program PMC4 with corresponding l2/l3 bus event for that >> bank. >> >> Commit 59029136d750 ("powerpc/perf: Add constraints for power9 l2/l3 bus events") >> enforced this rule in Power9. But this is not valid for >> Power10, since in Power10 Monitor Mode Control Register2 >> (MMCR2) has bits to configure l2/l3 event bits. Hence remove >> this PMC4 constraint check from power10. >> >> Since the l2/l3 bits in MMCR2 are not per-pmc, patch handles >> group constrints checks for l2/l3 bits in MMCR2. > >> Patch also updates constraints for threshold events in power10. > > That should be done in a separate patch please. Thanks mpe for checking the patch set. Sure, I will make threshold constraint changes as a separate patch and send next version > > cheers
diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c index f57f54f..0f4983e 100644 --- a/arch/powerpc/perf/isa207-common.c +++ b/arch/powerpc/perf/isa207-common.c @@ -311,9 +311,11 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) } if (unit >= 6 && unit <= 9) { - if (cpu_has_feature(CPU_FTR_ARCH_31) && (unit == 6)) { - mask |= CNST_L2L3_GROUP_MASK; - value |= CNST_L2L3_GROUP_VAL(event >> p10_L2L3_EVENT_SHIFT); + if (cpu_has_feature(CPU_FTR_ARCH_31)) { + if (unit == 6) { + mask |= CNST_L2L3_GROUP_MASK; + value |= CNST_L2L3_GROUP_VAL(event >> p10_L2L3_EVENT_SHIFT); + } } else if (cpu_has_feature(CPU_FTR_ARCH_300)) { mask |= CNST_CACHE_GROUP_MASK; value |= CNST_CACHE_GROUP_VAL(event & 0xff); @@ -349,7 +351,12 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT); } - if (cpu_has_feature(CPU_FTR_ARCH_300)) { + if (cpu_has_feature(CPU_FTR_ARCH_31)) { + if (event_is_threshold(event)) { + mask |= CNST_THRESH_CTL_SEL_MASK; + value |= CNST_THRESH_CTL_SEL_VAL(event >> EVENT_THRESH_SHIFT); + } + } else if (cpu_has_feature(CPU_FTR_ARCH_300)) { if (event_is_threshold(event) && is_thresh_cmp_valid(event)) { mask |= CNST_THRESH_MASK; value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h index dc9c3d2..4208764 100644 --- a/arch/powerpc/perf/isa207-common.h +++ b/arch/powerpc/perf/isa207-common.h @@ -149,6 +149,9 @@ #define CNST_THRESH_VAL(v) (((v) & EVENT_THRESH_MASK) << 32) #define CNST_THRESH_MASK CNST_THRESH_VAL(EVENT_THRESH_MASK) +#define CNST_THRESH_CTL_SEL_VAL(v) (((v) & 0x7ffull) << 32) +#define CNST_THRESH_CTL_SEL_MASK CNST_THRESH_CTL_SEL_VAL(0x7ff) + #define CNST_EBB_VAL(v) (((v) & EVENT_EBB_MASK) << 24) #define CNST_EBB_MASK CNST_EBB_VAL(EVENT_EBB_MASK)
In Power9, L2/L3 bus events are always available as a "bank" of 4 events. To obtain the counts for any of the l2/l3 bus events in a given bank, the user will have to program PMC4 with corresponding l2/l3 bus event for that bank. Commit 59029136d750 ("powerpc/perf: Add constraints for power9 l2/l3 bus events") enforced this rule in Power9. But this is not valid for Power10, since in Power10 Monitor Mode Control Register2 (MMCR2) has bits to configure l2/l3 event bits. Hence remove this PMC4 constraint check from power10. Since the l2/l3 bits in MMCR2 are not per-pmc, patch handles group constrints checks for l2/l3 bits in MMCR2. Patch also updates constraints for threshold events in power10. Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support") Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> --- arch/powerpc/perf/isa207-common.c | 15 +++++++++++---- arch/powerpc/perf/isa207-common.h | 3 +++ 2 files changed, 14 insertions(+), 4 deletions(-)