From patchwork Mon Apr 20 21:37:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Derrick X-Patchwork-Id: 1273777 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 495glL4vpRz9sSG for ; Tue, 21 Apr 2020 08:06:38 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 495glL16ZGzDqkB for ; Tue, 21 Apr 2020 08:06:38 +1000 (AEST) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=intel.com (client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=jonathan.derrick@intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=intel.com Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 495gdS531lzDqsK for ; Tue, 21 Apr 2020 08:01:32 +1000 (AEST) IronPort-SDR: IG2nfgJGEU129B47dZGM4bO8FBPBdUPSt1bxIjdCuW4UNtyS+2PKE14k88To886i1jQsjB4X7X kcIfZER1cPug== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Apr 2020 15:01:12 -0700 IronPort-SDR: NaBAspYZuGnSTQEfEZz9R/EbojjS+9L7WFqbqEMeVWAABLhwoBVpCJ/CdN5nfrfXocev3M49EF hB6ewiUK3MTQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,407,1580803200"; d="scan'208";a="455848368" Received: from unknown (HELO nsgsw-wilsonpoint.lm.intel.com) ([10.232.116.102]) by fmsmga005.fm.intel.com with ESMTP; 20 Apr 2020 15:01:10 -0700 From: Jon Derrick To: Bjorn Helgaas Subject: [PATCH v2 2/2] PCI/DPC: Allow Native DPC Host Bridges to use DPC Date: Mon, 20 Apr 2020 15:37:10 -0600 Message-Id: <1587418630-13562-3-git-send-email-jonathan.derrick@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1587418630-13562-1-git-send-email-jonathan.derrick@intel.com> References: <1587418630-13562-1-git-send-email-jonathan.derrick@intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kuppuswamy Sathyanarayanan , Rajat Jain , "Rafael J. Wysocki" , Frederick Lawler , Sam Bobroff , linux-pci@vger.kernel.org, Olof Johansson , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Bjorn Helgaas , Alex Williamson , "Patel, Mayurkumar" , Oliver O'Halloran , Keith Busch , Andy Shevchenko , Mika Westerberg , Jon Derrick Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The existing portdrv model prevents DPC services without either OS control (_OSC) granted to AER services, a Host Bridge requesting Native AER, or using one of the 'pcie_ports=' parameters of 'native' or 'dpc-native'. The DPC port service driver itself will also fail to probe if the kernel assumes the port is using Firmware-First AER. It's a reasonable expectation that a port using Firmware-First AER will also be using Firmware-First DPC, however if a Host Bridge requests Native DPC, the DPC driver should allow it and not fail to bind due to AER capability settings. Host Bridges which request Native DPC port services will also likely request Native AER, however it shouldn't be a requirement. This patch allows ports on those Host Bridges to have DPC port services. This will avoid the unlikely situation where the port is Firmware-First AER and Native DPC, and a BIOS or switch firmware preconfiguration of the DPC trigger could result in unhandled DPC events. Signed-off-by: Jon Derrick --- drivers/pci/pcie/dpc.c | 3 ++- drivers/pci/pcie/portdrv_core.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c index 7621704..3f3106f 100644 --- a/drivers/pci/pcie/dpc.c +++ b/drivers/pci/pcie/dpc.c @@ -284,7 +284,8 @@ static int dpc_probe(struct pcie_device *dev) int status; u16 ctl, cap; - if (pcie_aer_get_firmware_first(pdev) && !pcie_ports_dpc_native) + if (pcie_aer_get_firmware_first(pdev) && !pcie_ports_dpc_native && + !pci_find_host_bridge(pdev->bus)->native_dpc) return -ENOTSUPP; status = devm_request_threaded_irq(device, dev->irq, dpc_irq, diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index 50a9522..f2139a1 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -256,7 +256,8 @@ static int get_port_device_capability(struct pci_dev *dev) */ if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC) && pci_aer_available() && - (pcie_ports_dpc_native || (services & PCIE_PORT_SERVICE_AER))) + (pcie_ports_dpc_native || host->native_dpc || + (services & PCIE_PORT_SERVICE_AER))) services |= PCIE_PORT_SERVICE_DPC; if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM ||