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Wed, 30 Oct 2019 17:00:01 +0000 (GMT) Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 34DE72805C; Wed, 30 Oct 2019 17:00:01 +0000 (GMT) Received: from arbab-laptop.localdomain (unknown [9.53.179.210]) by b01ledav001.gho.pok.ibm.com (Postfix) with ESMTP; Wed, 30 Oct 2019 17:00:01 +0000 (GMT) Received: by arbab-laptop.localdomain (Postfix, from userid 152845) id 5562A4654A9; Wed, 30 Oct 2019 12:00:00 -0500 (CDT) From: Reza Arbab To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 04/11] powerpc/powernv/npu: Wire up pnv_npu_try_dma_set_bypass() Date: Wed, 30 Oct 2019 11:59:53 -0500 Message-Id: <1572454800-17976-5-git-send-email-arbab@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1572454800-17976-1-git-send-email-arbab@linux.ibm.com> References: <1572454800-17976-1-git-send-email-arbab@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-10-30_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1910300150 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Donnellan , Alexey Kardashevskiy , Oliver O'Halloran , Alistair Popple , Paul Mackerras , Thomas Gleixner , Christoph Hellwig Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Rework of pnv_pci_ioda_iommu_bypass_supported() dropped a call to pnv_npu_try_dma_set_bypass(). Reintroduce this call, so that the DMA bypass configuration of a GPU device is propagated to its corresponding NPU devices. Fixes: 2d6ad41b2c21 ("powerpc/powernv: use the generic iommu bypass code") Signed-off-by: Reza Arbab Cc: Christoph Hellwig --- arch/powerpc/platforms/powernv/pci-ioda.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index 8849218187d7..70e834635971 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -1833,14 +1833,13 @@ static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev, struct pnv_phb *phb = hose->private_data; struct pci_dn *pdn = pci_get_pdn(pdev); struct pnv_ioda_pe *pe; + bool bypass; if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) return false; pe = &phb->ioda.pe_array[pdn->pe_number]; - - if (pnv_ioda_pe_iommu_bypass_supported(pe, dma_mask)) - return true; + bypass = pnv_ioda_pe_iommu_bypass_supported(pe, dma_mask); /* * If the device can't set the TCE bypass bit but still wants @@ -1848,7 +1847,8 @@ static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev, * bypass the 32-bit region and be usable for 64-bit DMAs. * The device needs to be able to address all of this space. */ - if (dma_mask >> 32 && + if (!bypass && + dma_mask >> 32 && dma_mask > (memory_hotplug_max() + (1ULL << 32)) && /* pe->pdev should be set if it's a single device, pe->pbus if not */ (pe->device_count == 1 || !pe->pbus) && @@ -1859,10 +1859,14 @@ static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev, return false; /* 4GB offset bypasses 32-bit space */ pdev->dev.archdata.dma_offset = (1ULL << 32); - return true; + + bypass = true; } - return false; + /* Update peer npu devices */ + pnv_npu_try_dma_set_bypass(pdev, dma_mask); + + return bypass; } static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)